MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 260

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
9.3.5.2
The DMA reads back the true TCD.SADDR, TCD.DADDR, and TCD.NBYTES values if read while a
channel is executing. The true values of the SADDR, DADDR, and NBYTES are the values the
DMA_ENGINE is currently using in its internal register file and not the values in the TCD local memory
for that channel. The addresses (SADDR and DADDR) and NBYTES (decrements to 0 as the transfer
progresses) can give an indication of the progress of the transfer. All other values are read back from the
TCD local memory.
9.3.5.3
Preemption is only available when fixed arbitration is selected for group and channel arbitration modes. A
preemptable situation is when a preempt-enabled channel is running and a higher priority request becomes
active. When the DMA_ENGINE is not operating in fixed group, fixed channel arbitration mode, the
determination of the relative priority of the actively running and the outstanding requests become
undefined. Channel and/or group priorities are treated as equal (or more exactly, constantly rotating) when
round-robin arbitration mode is selected.
The TCD.ACTIVE bit for the preempted channel remains asserted throughout the preemption. The
preempted channel is temporarily suspended while the preempting channel executes one iteration of the
major loop. Two TCD.ACTIVE bits set at the same time in the overall TCD map indicates a higher priority
channel is actively preempting a lower priority channel.
The worst case latency when switching to a preempt channel is the summation of:
9.3.6
Channel linking (or chaining) is a mechanism where one channel sets the TCD.START bit of another
channel (or itself) that initiates a service request for that channel. This operation is automatically
performed by the DMA_ENGINE at the conclusion of the major or minor loop when properly enabled.
The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major
loop). The TCD.CITER.E_LINK field is used to determine whether a minor loop link is requested. When
enabled, the channel link is made after each iteration of the major loop except for the last. When the major
loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be
made.
For example, with the initial fields of:
9-40
•
•
•
TCD.citer.e_link= 1
TCD.citer.linkch= 0xC
TCD.citer value= 0x4
TCD.major.e_link= 1
TCD.major.linkch= 0x7
Arbitration latency (2 cycles)
Bandwidth control stalls (if enabled)
The time to execute two read/write sequences (including AHB bus holds; a system dependency
driven by the slave devices or the crossbar)
Channel Linking
Active Channel TCD Reads
Preemption Status
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor