MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 855

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.2.4.5
The Control Data Structure Segment (CTRLDSSEGMENT) register is not implemented on the MPC5125.
32.2.4.6
The Periodic Frame List Base Address (USB_PERIODICLISTBASE) register contains the beginning
address of the Periodic Frame List in the system memory. The host controller driver loads this register prior
to starting the schedule execution by the controller. The memory structure referenced by this physical
memory pointer is assumed to be 4 KB aligned. The contents of this register are combined with the
USB_FRINDEX register to enable the controller to step through the periodic frame list in sequence.
On the OTG module, this register is shared between the host and device mode functions. In host mode, it
is the USB_PERIODICLISTBASE register; in device mode, it is the USB_DEVICEADDR register. See
Section 32.2.4.7, “Device Address (USB_DEVICEADDR) Register (Non-EHCI),”
Freescale Semiconductor
Address: Base + 0x14C
Reset
Reset
FRINDEX
Field
W
W
R
R
16
0
0
0
0
0
Control Data Structure Segment Register (CTRLDSSEGMENT)
Periodic Frame List Base Address (USB_PERIODICLISTBASE) Register
Frame index. The value in this register increments at the end of each time frame (for example, microframe).
Bits [N– 3] are used for the frame list current index. This means that each location of the frame list is accessed
8 times (frames or microframes) before moving to the next index.
The value is the current frame number of the last frame transmitted. It is not used as an index.
Bits 2–0 indicate the current microframe.
17
0
0
0
0
1
18
0
0
0
2
Figure 32-19. USB Frame Index (USB_FRINDEX) Register
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-20. USB_FRINDEX field descriptions
20
4
0
0
0
21
0
0
0
5
22
0
0
0
6
23
0
0
0
7
Description
FRINDEX
24
8
0
0
0
25
9
0
0
0
Universal Serial Bus Interface with On-The-Go
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
for more information.
Access: User read/write
13
29
0
0
0
14
30
0
0
0
32-27
15
31
0
0
0