MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 930

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
The general processing model for the host controller's use of a queue head is simple:
If the host controller encounters errors during a transaction, the host controller sets one of the error
reporting bits in the queue head's status field. The status field accumulates all errors encountered during
the execution of a qTD (error bits in the queue head status field are sticky until the transfer [qTD] has
completed). This state is always written back to the source qTD when the transfer is complete. On transfer
(for example, buffer or halt conditions) boundaries, the host controller must auto-advance (without
software intervention) to the next qTD. Additionally, the hardware must be able to halt the queue so no
additional bus transactions occur for the endpoint and the host controller does not advance the queue.
An example host controller operational state machine of a queue head traversal is illustrated in
Figure
host controller must be able to advance the queue from the Fetch QH state to avoid all hardware/software
race conditions. This simple mechanism allows software to simply link qTDs to the queue head and
activate them, then the host controller always finds them if/when they are reachable.
32-102
•
•
•
•
32-61. This state machine is a model for how a host controller should traverse a queue head. The
Read a queue head
Execute a transaction from the overlay area
Write back the results of the transaction to the overlay area
Move to the next queue head
Figure 32-61. Host Controller Queue Head Traversal State Machine
!Active
MPC5125 Microcontroller Reference Manual, Rev. 2
!Active and I-bit
Advance
Queue
Halted
or
Active
!Halted
!Active
and
!Active
Fetch QH
Write Back
Follow QH
Transaction
Horizontal
Pointer
Execute
Start
qTD
Active and !Halted
Active
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