MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 502

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (I
The frequency divide register determines the SCL or serial bit-clock frequency.
to select FDR bits that produce an appropriate SCL. The following relationships illustrate the connection
between
Figure 19-10
For standard mode I
19-10
1. SCL (in kHz) = (1/1000) × [IPS clock speed (in Hz)]/(SCL Period)
2. SDA Hold Time (in µs) = 1000 × (SDA Hold/SCL Period)/[SCL (in kHz)]
3. SCL Hold Time of START (in µs) = 1000 × (SDA Hold of START/SCL Period)/[SCL (in kHz)]
4. SCL Hold Time of STOP (in µs) = 1000 × (SDA Hold of STOP/SCL Period))/[SCL (in kHz)]
and
and
and
System
Table 19-6
Clock
SDA
SDA
SCL
SCL
illustrates the relationship between the IPS clock and the I
2
C)
2
and the signals in the I
START Condition
C, the I
SDA Hold
Figure 19-10. Timing Diagram of I
2
C specification states:
MPC5125 Microcontroller Reference Manual, Rev. 2
(0.3 µs ≤ SDA Hold Time ≤ 3.45 µs)
(SCL Hold of START ≥ 4 µs)
(SCL Hold of STOP ≥ 4 µs)
(SCL ≤ 100 kHz)
SCL Hold of START
2
C timing specification.
SCL Period
SCL Hold of STOP
2
C Signal Relationships
2
C signals.
STOP Condition
Table 19-6
Freescale Semiconductor
must be used
Eqn. 19-1
Eqn. 19-2
Eqn. 19-3
Eqn. 19-4