MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 719

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

transmitter or receiver is enabled or not, as opposed to the SPI behavior.
show the calculation.
When the FrameSync is an output, the
the number of BCLK cycle during the FrameSync signal is active. The default reset value for this register
is 0x00. Therefore, the default FrameSync width is one BCLK. See
25.5.2.3
The PSC supports the full duplex soft modem mode, data is received and transmitted at the same time. To
start the full duplex transmission, the Tx and the Rx must be enabled by writing the according value to the
CR register. It’s also possible to only use the receiver. For this case, only the Rx enable bit in the CR
register must be set to one. However, it’s not possible to use the transmitter without the receiver. To
transmit data only, the receiver must be enabled. The received data and the according status and interrupt
bits can be ignored.
If the receiver is enabled, the PSC samples data from the receive line after detecting the start of frame
condition. The receiver converts the serial data from the RX line to parallel data words and writes the data
to the RxFIFO. The data word length depends on the programmed word length. If no data exists on the Rx
line, the receiver writes zeros to the RxFIFO until the data word width was reached. The receiver waits
until the next start of frame condition is detected. The transmitter converts the parallel data from the
TxFIFO to a serial data stream on the TX line. If the TxFIFO is empty during the transmit state, the Tx
line is zero. If the last bit of the data word is sent, the transmitter waits until the next start of frame condition
is detected.
When SICR[GenClk] = 1, the PSC is in master mode and generates the BCLK and the FrameSync signal
from the internal clock system, as described in
Generation.”
Figure 25-47
parameters to define the interface are follows:
Freescale Semiconductor
•
Frame Sync Polarity SICR[SyncPol]. The leading edge is defined as a rising edge if bit
SICR[SyncPol] equals 1 or a falling edge if SICR[SyncPol] equals 0.
Transmitting and Receiving in Soft Modem Codec Mode
shows a codec interface diagram example for soft modem master mode. The different
MPC5125 Microcontroller Reference Manual, Rev. 2
FrameSync Length = Frame SyncDiv[0:7]
BCLK =
Frame sync width = CTUR[0:7]
CTUR
BCLKDiv[0:15] +1
register can program the pulse width. This register defines
Section 25.5.2.2, “Codec Clock and FrameSync
MCLK
+
1
Equation
+
Equation 25-3
1
Programmable Serial Controller (PSC)
25-5.
and
Equation 25-4
Eqn. 25-3
Eqn. 25-4
Eqn. 25-5
25-41