MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 556

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
21.2.1.2.4
21-16
Address: Base + 0x10C
Reset
Reset
Field
Field
BPT
DAI
AIE
NIE
ME
RC
RF
W
W
R
R
16
0
0
0
0
0
SCLPC Enable (LPC_SCLPC_E) Register
Disable auto increment. Normally, SCLPC and LPC present sequential incrementing addresses to the device
as the packet proceeds. If the device is operating as a single address FIFO, the DAI bit should be set to 1.
When set, addresses to the device are stuck at start_address for every transaction.
For DAI operation, the BPT field must be set to the port size of the device.
Bytes per transaction that indicates the number of bytes per transaction. The only valid entries in this field are
1, 2, 4, 8, 16, 24, 32, 40, 48, and 56.
Start_address and packet_size values must be aligned/multiples of BPT or multiples of 8. BPT should be set
to the device port size for DAI operation.
Reset controller. This bit allows for a software reset of the SCLPC state machine. Writing a 1 to this bit resets
the SCLPC state machine. Reset is maintained as long as this bit is high. Software must write this bit low to
release the reset and start operation.
Note: Although RC does not reset this register interface, it does clear interrupt and interrupt status conditions.
Never reset the SCLPC Controller during a transaction (TX or RX).
Reset FIFO. This is the FIFO software reset bit. Writing a 1 to this bit resets the SCLPC FIFO. For normal
operation, the FIFO must not be in reset. Resetting the FIFO clears the FIFO of data and resets its read/write
pointers and the status bits, but it does not disturb previously programmed alarm and granularity settings.
Note: It is recommended that software set and clear the RC and RF bits prior to programming and starting a
Abort interrupt enable. If set, and a FIFO error occurs during packet transmission, a CPU interrupt from
SCLPC is generated. In any case, the packet is terminated and an abort status bit is set.
Normal interrupt enable. If set, this bit enables a CPU interrupt to occur at the end of a normally terminated
packet. There is also an NT status bit that sets in any case.
Master enable. This bit must be set to 1 to generate a restart to the SCLPC state machine. Restart is achieved
by writing 1 to byte 0 of the packet_size register. This ME bit must also be set for a restart to occur.
Note: If ME is low (inactive), it also clears interrupt and interrupt status.
17
0
0
0
0
1
packet.
18
0
0
0
0
2
Table 21-14. LPC_SCLPC_C field descriptions (continued)
Figure 21-14. SCLPC Enable (LPC_SCLPC_E) Register
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 21-15. LPC_SCLPC_E field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
AIE
22
0
0
0
6
NIE
RC
23
0
0
7
Description
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
ME
RF
15
31
0
0