MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 308

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Display Interface Unit (DIU)
FP_V pulse of the current frame (set it to greater than 0) or the host does not have enough time to properly
reprogram the DIU. Use the VSYNC_WB interrupt for mode 3.
For operating mode with writeback operation, a VSYNC_WB interrupt can be used to find the end of a
writeback frame. To enable the DIU to work on the next writeback frame, the user need to reprogram the
DESC_1/DESC_2/DESC_3 pointers for related planes, and the WB_MEM_ADDR register after the
VSYNC_WB interrupt is detected.
10.5.4
A parameter error exception occurs under the conditions detailed in
interrupt is issued to the host. On reception of a PARERR interrupt, the user should turn off the DIU,
correct the wrong parameters, and then turn it on again (by programming the DIU_MODE register). The
DIU is initialized internally.
10.5.5
In a heavily loaded system, the DIU may experience buffer underrun errors because of long DRAM access
latency. To eliminate buffer underrun issues, the user should program the MPC5125 DRAM controller
priority manager so that the DIU has higher priority compared to the other masters, or program the priority
manager and the DIU PLUT register to enable dynamic DIU priority escalation so that the DIU priority
can be high enough while its buffer filling is low.
If a single buffer underrun occurs and it is short, the DIU may repeat the pixel before the underrun and then
recover automatically when the underrun is gone to minimize impact to the display. Slight underrun
error(s) do not propagate between frames, but if underrun errors take place frequently, the user should turn
off the DIU, escalate the DIU priority (if necessary), and then turn it on again so that it can display
normally.
10-46
LS_BF_VS Interrupt
Recovering from Parameter Error
Recovering from Underrun Error
DIU load cursor, palette, gamma
Area Descriptors for FRAME n
FP_V
VSYNC Interrupt
PW_V
Figure 10-51. Synchronizing the Host and the DIU
DIU Window
MPC5125 Microcontroller Reference Manual, Rev. 2
BP_V
Start of
FRAME n
LS_BF_VS
CPU program the
Host Window
RES_V
registers for FRAME n + 1
FP_V
VSYNC
Table
PW_V
10-43. If enabled, a PARERR
BP_V
Freescale Semiconductor
Start of
FRAME n + 1