MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 111

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.1.3
The System Clock Control Register 2 (SCCR2), shown in
configurable clock ratio.
Freescale Semiconductor
Address: Base + 0x08
FIFOC_EN
FEC1_EN
FEC2_EN
Reset
Reset
DDR_EN
Field
W
W
R DIU
R
_EN
16
0
0
0
0
System Clock Control Register 2 (SCCR2)
FIFOC Clock Enable
0 Disable
1 Enable
Note: If one of the PSC is used, the FIFOC clock must be enabled.
FEC1 Clock Enable
0 Disable
1 Enable
MDDRC Clock Enable
0 Disable
1 Enable
FEC2 Clock Enable
0 Disable
1 Enable
17
0
0
0
0
1
MEM
_EN
18
1
0
0
2
Figure 5-8. System Clock Control Register 2 (SCCR2)
USB1
_EN
19
Table 5-7. SCCR1 field descriptions (continued)
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
USB2
_EN
20
4
0
0
0
_EN
I2C
21
0
0
0
5
AUTO
_EN
22
0
0
0
6
SDHC1
_EN
23
0
0
0
7
Description
Figure
24
8
0
0
0
0
25
9
0
1
0
0
5-8, controls device units with a
10
26
0
0
0
0
11
27
0
0
0
0
Clocks and Low-Power Modes
_ EN
IIM
12
28
0
0
0
Access: User read/write
13
29
0
0
0
0
SDHC
2_EN
14
30
0
0
0
15
31
5-11
0
0
0
0