MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 800

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
In addition, this block also manages the burst request to the external DMA controller, internal register
write-error detection, read wait handling of SDIO, and all IP related output responses.
28.4.2.1
If a transfer is in progress, the SDHC generates DMA requests according to the FIFO status. During read
operations, the SDHC generates DMA requests if one of the data FIFOs is full. During write operations,
the SDHC generates DMA requests if one of the data FIFOs is empty.
To avoid buffer under-run conditions during a write operation, the MMC_SD_CLK stops automatically
when both buffers are empty. After the DMA or CPU completes writing data into one of the buffers,
MMC_SD_CLK resumes automatically to continue the data transfer.
Similarly, to avoid buffer over-flow during read operations, the MMC_SD_CLK stops automatically when
both buffers are full. After the DMA or CPU moves the data out of the buffer, the MMC_SD_CLK resumes
automatically to continue the data transfer.
28.4.3
This controller provides the SDIO-IRQ and read/wait service handling, card detection, command response
handling, all SDHC interrupt managing, and it contains the register table. See
diagram for the memory controller.
28-28
Memory Controller
DMA Request
R/W from Appl.
R/W from Host
Handshake to Host
Host Status
EFB/FFB Control
DMA_INF
Empty/Full
Control
FIFO
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 28-19. DMA Interface Block
FIFO Status
FSM
Access Handler
Host/DMA R/W
Block Counter
Byte Counter/
Multiplexer
Data Path
ram_addr
ram_rw
ram_data
EFB, FFB for Appl.
EFB, FFB for Host
mmc_dreq
data_in
data_out
Figure 28-20
Reg File
RAM
32x4
Freescale Semiconductor
for the block