MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 327

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3.2.8
11.3.2.9
Freescale Semiconductor
DQS MASTER COUNT 2 Delay count output by the controller for the first DQS master to code for 1/4 CSB clock delay.
DQS MASTER COUNT 1 Delay count output by the controller for the second DQS master to code for 1/4 CSB clock delay.
DQS_SLAVE_[3:0]_
Address: Base + 0x0040
Address: Base + 0x0060
OFFSET_TIME
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
Field
Field
16
16
0
0
0
0
0
0
0
0
0
DRAM_TIME_CCD
DQS Delay Status (DQS_DELAY_STATUS) Register
DDR Extra Attributes (EXTRA_ATTRIB) Register
_OTHER[3:0]
17
17
0
0
0
0
0
0
0
1
1
There is a separate field for each DQS input to the controller. These fields code for an offset counted in
time units.
This register can be used to advance or delay the read strobe. Negative values advance the read strobe,
positive values retard the read strobe.
Time delay coded = [field value (2-complement)] × Tdram-clock/256.
The applied offset range for a 200 MHz clock is approximately ± 290 ps.
Figure 11-17. DQS Delay Status (DQS_DELAY_STATUS) Register
Figure 11-18. DDR Extra Attributes (EXTRA_ATTRIB) Register
Table 11-15. DQS_CONFIG_OFFSET_TIME field descriptions
18
18
0
0
0
0
0
0
0
2
2
Table 11-16. DQS_DELAY_STATUS field descriptions
19
19
0
0
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
4
0
0
4
0
0
0
DRAM_TIME_WTR1
21
_OTHER
21
0
0
0
0
0
5
5
22
22
0
0
0
0
0
6
6
23
23
0
0
0
0
0
7
7
DQS MASTER COUNT 2[11:0]
DQS MASTER COUNT 1[11:0]
Description
CON
FIG_
SDR
Description
24
24
8
0
0
8
0
0
0
CAS3
CON
FIG_
25
25
9
0
0
9
0
0
0
CON
FIG_
A15
10
26
10
26
0
0
0
0
0
11
27
11
27
0
0
0
0
0
0
DRAM_CS_SELECT[3:0]
12
28
12
28
0
0
0
0
0
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
0
0
DRAM Controller
14
30
14
30
0
0
0
0
0
11-19
15
31
15
31
0
0
0
0
0