MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 743

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.2.1.5
Freescale Semiconductor
Address: Base + 0x90 (PSCn_TX_IMR)
MEM ERROR
DATA READY
Reset
Reset
ORERR
URERR
ALARM
EMPTY
FULL
Field
Field
W
W
R
R
Base + 0xD0 (PSCn_RX_IMR)
16
0
0
0
0
0
Interrupt Mask Register (IMR)
Underrun Error. This bit is identical to the ORERR bit in the SR register. If the corresponding bit in the IMR
register is also set, an interrupt is generated. Writing 1 to this bit clears the interrupt.
FIFO Alarm. This bit is identical to the ALARM bit in the SR register. If the corresponding bit in the IMR register
is also set, an interrupt is generated. Writing 1 to this bit clears the interrupt.
FIFO Full. This bit is identical to the FULL bit in the SR register. If the corresponding bit in the IMR register is
also set, an interrupt is generated. Writing 1 to this bit clears the interrupt.
FIFO Empty. This bit is identical to the EMPTY bit in the SR register. If the corresponding bit in the IMR register
is also set, an interrupt is generated. Writing 1 to this bit clears the interrupt.
Memory Access Error
0 The memory access error status has no effect on the interrupt line.
1 Enable the interrupt for memory access error.
Data Ready
0 The DATA READY status has no effect on the interrupt line.
1 Enable the interrupt for DATA READY status.
Overrun Error
0 The overrun error status has no effect on the interrupt line.
1 Enable the interrupt for overrun error.
17
0
0
0
0
1
18
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 26-7. ISR field descriptions (continued)
Figure 26-6. Interrupt Mask Register (IMR)
20
4
0
0
0
0
Table 26-8. IMR field descriptions
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
ERROR
MEM
25
9
0
0
0
READY
DATA
10
26
0
0
0
PSC Centralized FIFO Controller (FIFOC)
ERR
OR
11
27
0
0
0
ERR
UR
12
28
0
0
0
Access: User read/write
ALARM FULL EMPTY
13
29
0
0
0
14
30
0
0
0
15
31
26-9
0
0
0