MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 117

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.1.8
The PSC0 clock control register, shown in
MCLK divider enable, the PSC0 MCLK divider source, and the PSC0 MCLK source.
the bit fields of P0CCR.
Freescale Semiconductor
Address: Base + 0x18
Address: Base + 0x1C
MCLK_DIV
Reset
Reset
Reset
Reset
BIT0x0
PSC0_
Field
Field
W
W
W
W
R
R
R
R
PSC0_MCLK
16
16
0
0
1
_0_SRC
0
0
0
PSC0 Clock Control Register (P0CCR)
MCLK_DIV Divider Ratio
Note: The maximum supported frequency for f
A value of 0x0000 bypasses the divider.
Note: This value can only be changed when the value of MCLK_EN = 0.
17
17
0
0
1
0
1
1
f
mclk_out
18
18
0
0
1
0
0
2
2
= f
mclk_src
Figure 5-13. PSC0 Clock Control Register (P0CCR)
19
19
0
0
1
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 5-12. Bread Crumb Register (BCR)
/ (MCLK_DIV + 1)
Table 5-13. P0CCR field descriptions
20
20
4
0
0
4
1
0
0
Table 5-12. BCR field descriptions
21
21
0
0
1
0
0
5
5
Figure
PSC0_MCLK_DIV
22
22
0
0
1
0
0
6
6
5-13, controls the PSC0 MCLK divider ratio, the PSC0
23
23
0
0
1
0
0
7
7
mclk_out
Description
Description
MCLK_
PSC0_
1_SRC
24
24
8
0
0
8
1
0
is the IP Bus frequency.
25
25
9
0
0
9
1
0
0
10
26
10
26
0
0
1
0
0
11
27
11
27
0
0
1
0
0
Clocks and Low-Power Modes
12
28
12
28
0
0
1
0
0
Access: User read/write
Access: User read/write
Table 5-13
13
29
13
29
0
0
1
0
0
14
30
14
30
0
0
1
0
0
defines
MCLK
0_EN
15
31
15
31
5-17
0
0
0
0
0