MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 904

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.5.6.3
The nine doublewords in this area represent a transaction working space for the host controller. The general
operational model is that the host controller can detect whether the overlay area contains a description of
an active transfer. If it does not contain an active transfer, it follows the queue head horizontal link pointer
to the next queue head. The host controller never follows the next transfer queue element or alternate queue
element pointers unless it is actively attempting to advance the queue. For the duration of the transfer, the
host controller keeps the incremental status of the transfer in the overlay area. When the transfer is
complete, the results are written back to the original queue element.
The doubleword of a queue head contains a pointer to the source qTD currently associated with the
overlay. The host controller uses this pointer to write back the overlay area into the source qTD after the
transfer is complete.
The doublewords 4-11 of a queue head are the transaction overlay area. This area has the same base
structure as a queue element transfer descriptor. The queue head utilizes the reserved fields of the page
pointers to implement tracking the state of split transactions.
This area is characterized as an overlay because when the queue is advanced to the next queue element,
the source queue element is merged onto this area. This area serves an execution cache for the transfer.
32-76
Current qTD
C-mask
µFrame
µFrame
S-mask
Pointer
Field
Field
15:8
31:5
7:0
4:0
Transfer Overlay
This field is ignored by the host controller unless the EPS field indicates this device is a low- or full-speed device
and this queue head is in the periodic list. This field (along with the active and SplitX-state fields) is used to
determine during which micro-frames the host controller should execute a complete-split transaction. When the
criteria for using this field are met, a zero value in this field has undefined behavior. This field is used by the
host controller to match against the three low-order bits of the USB_FRINDEX register. If the USB_FRINDEX
register bits decode to a position where the µFrame C- mask field is a one, this queue head is a candidate for
transaction execution. There may be more than one bit in this mask set.
Interrupt Schedule Mask. This field is used for all endpoint speeds. Software should set this field to a zero when
the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint.
The host controller uses the value of the three low-order bits of the USB_FRINDEX register as an index into a
bit position in this bit vector. If the µFrame S-mask field has a one at the indexed bit position, this queue head
is a candidate for transaction execution. If the EPS field indicates the endpoint is a high-speed endpoint, the
transaction executed is determined by the PID_Code field contained in the execution area. This field is also
used to support split transaction types such as Interrupt (IN/OUT). This condition is true when this field is
non-zero and the EPS field indicates this is either a full- or low-speed device. A zero value in this field, in
combination with existing in the periodic frame list, has undefined results.
Current Element Transaction Descriptor Link Pointer. This field contains the address Of the current transaction
being processed in this queue and corresponds to memory address signals [31:5], respectively.
Reserved. These bits are ignored by the host controller when using the value as an address to write data. The
actual value may vary depending on the usage.
Table 32-63. Endpoint Capabilities: Queue Head doubleword 2 (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-64. Current qTD Link Pointer
Description
Description
Freescale Semiconductor