MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 415

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
OCPW
Field
OCT
ICM
ICT
CE
Output Compare Pulse Width. Applies to OC Pulse types only. This field specifies the number of IP bus clocks
(non-prescaled) to create a short output pulse at each Output Event. This pulse is generated at the end of the
OC period and overlays the next OC period (rather than adding to the period).
Output Compare Type. Describes action to occur at each output compare event, as follows:
00 Special case, output is immediately forced low without respect to each output compare event.
01 Output pulse highs, initial value is low (OCPW field applies).
10 Output pulses low, initial value is high (OCPW field applies).
11 Output toggles.
GPIO modalities can be used to achieve an initial output state prior to enabling OC mode. It is important to
move directly from one GPIO output mode to another OC mode and not to pass through the Timer_MS=000
state.
To prevent the Internal Timer Mode from engaging during the GPIO state, CE bit should be held low during
the configuration steps.
GPIO initialization is needed when presetting a Timer I/O to 1 in conjunction with a simple toggle OCT setting.
Note: For Stop Mode operation (see the STOP_CONT bit in this table) it is necessary to pass through the
Input Capture Mode—describes the input capture sub-mode as follows:
00 Normal input capture submode.
01 Up submode as well as normal input capture submode. Timer up/down counter increases one if it detects
10 Updown submode as well as input capture submode. Timers must be used in pairs. Timer 0 is paired with
11 Rotary submode as well as input capture submode. When an IC event is detected on Timer 0, the Timer
The IC event type is defined by the ICT field.
Note: The up/down counter value can be read from the
Input Capture Type. Describes the input transition type required to trigger an input capture event, as follows:
00 Any input transition causes an IC event.
01 IC event occurs at input rising edge.
10 IC event occurs at input falling edge.
11 IC event occurs at any input pulse (i.e., at 2nd input edge).
Note: For ICT 11 (pulse capture), status register records only the pulse width.
Counter Enable. Bit enables or resets the internal counter during Internal timer modes only. CE must be high
to enable these modes. If low, counter is held in reset.
This bit is secondary to the timer mode select bits (Timer_MS). If the Timer_MS contains 1XX, the internal
timer modes are enabled. CE can then enable or reset the internal counter without changing the Timer_MS
field.
GPIO operation is also available in this mode. 1 = enabled
IC event.
Timer 1, Timer 2 is paired with Timer 3, Timer 4 is paired with Timer 5 and Timer 6 is paired with Timer 7.
For example, the timer0 up/down counter increases by one if timer0 detects IC event. The Timer 0 up/down
counter decreases by one if timer1 detects an IC event. The timer 0 up/down counter remains unchanged
if an IC event occurs on both channels during a single prescaled clock count. Timers 2 and 3, Timers 4
and 5, and Timers 6 and 7 operate in a similar fashion.
0 up/down counter is incremented by 1 if Timer 1 is driven to a logic 0. the Timer 0 up/down counter
decrements by 1 if Timer 1 is driven to a logic 1. Timers 2 and 3, Timers 4 and 5 and Timers 6 and 7
operate in a similar fashion. When up/down counter overflow or underflow occurs, a CPU interrupt can be
generated if the interrupt enable bit is set.
mode_sel = 0 state to restart the output compare counters with their programmed values. See prescale
and count fields in
(GPT_COUNTER) Registers,”
is independent of the IC counter, which runs when enabled and latches the value when the IC event
happens. Normally counter means IC counter (input capture counter) when timer is in Input Capture
mode.When changing from one submode into another submode, the TIMER should be disabled.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 15-3. GPT_MODE Field Descriptions
Section 15.1.1, “Modes of Operation.”
bits 16-31. The value represents how many times an event happens. It
Description
GPT0 – GPT7 Input and Up/Down Counter Output
General Purpose Timers (GPT)
15-5