MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 932

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
This state is entered from the FetchQHD state if the overlay Active and Halt bits are set to zero. On entry
to this state, the host controller determines which next pointer to use to fetch a qTD, fetches a qTD and
determines whether or not to perform an overlay. If the I-bit is a one and the Active bit is a zero, the host
controller immediately skips processing of this queue head, exits this state and uses the horizontal pointer
to the next schedule data structure. If the field Bytes to Transfer is not zero and the T-bit in the Alternate
Next qTD Pointer is set to zero, then the host controller uses the Alternate Next qTD Pointer. Otherwise,
the host controller uses the Next qTD Pointer. If Next qTD Pointer’s T-bit is set to 1, then the host
controller exits this state and uses the horizontal pointer to the next schedule data structure.
Using the selected pointer the host controller fetches the referenced qTD. If the fetched qTD has its Active
bit set to a one, the host controller moves the pointer value used to reach the qTD (Next or Alternate Next)
to the Current qTD Pointer field, then performs the overlay. If the fetched qTD has its Active bit set to a
zero, the host controller aborts the queue advance and follows the queue head's horizontal pointer to the
next schedule data structure. The host controller performs the overlay based on the following rules:
The host controller exits this state when it has committed the write to the queue head.
32.6.9.3
The host controller enters this state from the Fetch Queue Head state only if the Active bit in Status field
of the queue head is set to a one.
On entry to this state, the host controller executes a few pre-operations, then checks some pre-condition
criteria before committing to executing a transaction for the queue head.
The pre-operations performed and the pre-condition criteria depend on whether the queue head is an
interrupt endpoint. The host controller can determine that a queue head is an interrupt queue head when
the queue head’s S-mask field contains a non-zero value. It is the responsibility of software to ensure the
S-mask field is appropriately initialized based on the transfer type. There are other criteria that must be
met if the EPS field indicates that the endpoint is a low- or full-speed endpoint, see
“Split Transactions for Asynchronous Transfers,”
32-104
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The value of the data toggle (dt) field in the overlay area depends on the value of the data toggle
control (dtc) bit.
If the EPS field indicates the endpoint is a high-speed endpoint, the Ping state field is preserved by
the host controller. The value of this field is not changed as a result of the overlay.
C-prog-mask field is set to zero (field from incoming qTD is ignored, as is the current contents of
the overlay area).
Frame Tag field is set to zero (field from incoming qTD is ignored, as is the current contents of the
overlay area).
NakCnt field in the overlay area is loaded from the RL field in the queue head's Static Endpoint
State.
All other areas of the overlay are set by the incoming qTD.
Interrupt Transfer Pre-condition Criteria
If the queue head is for an interrupt endpoint (non-zero S-mask field), then the
USB_FRINDEX[2:0] field must identify a bit in the S-mask field that has a one in it. For example,
Execute Transaction
MPC5125 Microcontroller Reference Manual, Rev. 2
and
Section 32.6.11.2, “Split Transaction Interrupt.”
Section 32.6.11.1,
Freescale Semiconductor