MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 548

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
21-8
ADDRM
ALEN
WTyp
Field
WS
WO
BM
DS
RS
ALE length
00 ALE width is one LPC clock.
01 ALE width is two LPC clocks.
10 ALE width is three LPC clocks.
11 ALE width is four LPC clocks.
Note: ALE length configures not only the width of the ALE assertion, but also the width of the isolation cycle
Data size field that represents the device data bus size (in bytes):
00 1byte.
01 2 bytes.
10 Reserved.
11 4 bytes.
Note:
Burst mode
0 Synchronous burst mode.
1 Asynchronous burst mode (page mode).
Note: The asynchronous burst mode setting is only valid for non-muxed transactions. If this bit is set and
Note: This bit has no influence if bursting (read or write) is not enabled.
Address mode
0 Byte addressing.
1 Short or word addressing.
An 8-bit data bus always uses a byte addressing.
Note:
Wait state type bits that define the application of wait states contained in the WaitP and WaitX fields, as
follows:
00 WaitX is applied to read and write cycles (WaitP is ignored)
01 WaitX is applied to read cycles; WaitP is applied to write cycles
10 WaitX is applied to reads; WaitP/WaitX (16-bit value) is applied to writes
11 WaitP/WaitX (as a full 16-bit value) is applied to reads and writes
Write swap bit. If high, endian byte swapping occurs during writes to a device.
0 Swapping cannot occur.
1 Swapping can occur.
A 2-byte swap is AB to BA; a 4-byte swap is ABCD to DCBA.
Note: Transactions at less than the defined port size (i.e., data size) apply swapping rules as above, according
Read swap bit. Same as WS, but swapping is done when reading data from a device.
0 Swapping cannot occur.
1 Swapping can occur.
Note: Transactions at less than the defined port size (i.e., data size) apply swapping rules as above, according
Write-only bit. If the bit is high, the device is treated as a write-only device. An attempted read access can
results in an interrupt (as dictated by the Chip Select Control (LPC_CSC) Register IE bit). In any case, no
transaction is presented to the device.
• For 8-bit devices, this bit has no effect
• For 16-bit devices, byte swapping can occur
• For 32-bit devices (possible in muxed mode only), byte swapping can occur
between ALE deassertion and CS assertion.
Table 21-26
muxed mode is enabled, a synchronous burst is performed.
Table 21-26
to the current transaction size.
to the current transaction size.
Table 21-4. LPC_CSnC field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
and
and
Table 21-30
Table 21-30
show on which AD lines the data is located.
show on which AD/AX lines the address is located.
Description
Freescale Semiconductor