MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 900

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.5.5.4
The last five doublewords of a queue element transfer descriptor is an array of physical memory address
pointers. These pointers reference the individual pages of a data buffer.
System software initializes Current Offset field to the starting offset into the current page, where current
page is selected via the value in the C_Page field.
32.5.6
Figure 32-49
32-72
31:12
11:0
Bit
Current Offset
Buffer Pointer
(Pages 1-4)
(Page 0)/—
(page n)
Queue Head
Name
qTD Buffer Page Pointer List
shows the queue head structure.
Each element in the list is a 4K page aligned physical memory address. The lower 12 bits in each
pointer are reserved (except for the first one), as each memory pointer must reference the start of
a 4K page. The field C_Page specifies the current active pointer. When the transfer element
descriptor is fetched, the starting buffer address is selected using C_Page (similar to an array index
to select an array element). If a transaction spans a 4K buffer boundary, the host controller must
detect the page-span boundary in the data stream, increment C_Page and advance to the next
buffer pointer in the list, and conclude the transaction via the new buffer pointer.
This field is reserved in all pointers except the first one (that is, Page 0). The host controller should
ignore all reserved bits. For the page 0 current offset interpretation, this field is the byte offset into
the current page (as selected by C_Page). The host controller is not required to write this field back
when the qTD is retired. Software should ensure the reserved fields are initialized to zeros.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-60. qTD Buffer Pointer
Description
Freescale Semiconductor