MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 380

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3.5.13 Physical Address Low (ETH_PADDR1) Register
The Physical Address Low (ETH_PADDR1) register contains the lower 32 bits (bytes 0, 1, 2, 3) of the
48-bit address used in the address recognition process to compare with the destination address (DA) field
of receive frames with an individual DA. In addition, this register is used in bytes 0–3 of the 6-byte source
address field when transmitting pause frames. This register is not reset and must be initialized by the user.
14-24
Address: Base + 0x0E4
RFC_PAUSE
TFC_PAUSE
Reset
Reset
FDEN
Field
HBC
GTS
W
W
R
R
16
0
0
0
This read-only status bit is asserted when a full-duplex flow control pause frame has been received and the
transmitter is paused for the duration defined in this pause frame. This bit automatically clears when the pause
duration is complete.
This bit is asserted to transmit a pause frame. When this bit is set, the MAC stops transmission of data frames
after the current transmission is complete. At this time, the GRA interrupt in the INTR_EVENT register is
asserted. With transmission of data frames stopped, the MAC transmits a MAC control pause frame. Next, the
MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the transmitter is paused due to
assertion of GTS or reception of a pause frame, the MAC may continue to transmit a MAC control pause
frame.
Full-duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs. This bit
should be modified only when ETHER_EN bit of the ETH_ECNTRL register is deasserted.
Heartbeat control. If set, the heartbeat check is performed following the end of transmission and the HB bit in
the status register is set if the collision input does not assert within the heartbeat window. This bit should be
modified only when the ETHER_EN bit of the ETH_ECNTRL register is deasserted.
Graceful transmit stop. When this bit is set, the MAC stops transmission after completion of any frame
currently being transmitted, and the GRA interrupt in the INTR_EVENT register is asserted. If frame
transmission is not currently underway, the GRA interrupt is asserted immediately. After transmission is
complete, a restart can be accomplished by clearing the GTS bit. The next frame in the transmit FIFO is then
transmitted. If an early collision occurs during transmission when GTS equals 1, transmission stops after the
collision. The frame is transmitted again after GTS is cleared. There may be old frames in the transmit FIFO
that are transmitted when GTS is reasserted. To avoid this, deassert ETHER_EN bit of the ETH_ECNTRL
register following the GRA interrupt.
17
0
0
1
Figure 14-14. Physical Address Low (ETH_PADDR1) Register
18
0
0
2
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-17. ETH_X_CNTRL field descriptions
20
4
0
0
21
0
0
5
22
0
0
6
23
PADDR1
PADDR1
0
0
7
Description
24
8
0
0
25
9
0
0
10
26
0
0
11
27
0
0
12
28
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
14
30
0
0
15
31
0
0