MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 184

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.4.7.3
The Transmit Single Byte IFR (TSIFR) bit in BDLC Control Register 2 is used to transmit Type 1 and Type
2 IFRs onto the SAE J1850 bus. If this bit is set after a byte is loaded into the BDLC Data Register, the
BDLC module attempts to send that byte, preceded by the appropriate Normalization Bit, as a single byte
IFR without a CRC. If arbitration is lost, the BDLC module automatically attempts to transmit the byte
again (without a Normalization Bit) as soon as the byte winning arbitration completes transmission.
Attempts to transmit the byte continue until the byte is successfully transmitted, the TEOD bit is set by the
user, or an error is detected on the bus.
The user must set the TSIFR bit before the EOD following the main part of the message frame is received,
or no IFR transmit attempts are made for the current message. If another node does transmit an IFR to this
message or a reception error occurs, the TSIFR bit is cleared. If not, the IFR is transmitted after the EOD
of the next received message.
The TSIFR bit is automatically cleared after the EOD following one or more IFR bytes has been received
or an error is detected on the bus.
6.4.7.4
The Transmit Multi-Byte IFR 1 (TMIFR1) bit is used to transmit an SAE J1850 Type 3 IFR with a CRC
byte appended. If this bit is set after the user has loaded the first byte of a multi-byte IFR into the BDLC
Data Register, the BDLC module begins transmitting that byte, preceded by the appropriate Normalization
Bit, onto the SAE J1850 bus. After this happens, a TDRE interrupt occurs, indicating to the user that the
next IFR byte should be loaded into the BDLC Data Register. When the last byte to be transmitted is
written to the BDLC Data Register, the user sets the TEOD bit. This causes a CRC byte and an EOD
symbol to be transmitted following the last IFR byte.
As with the TSIFR bit, the TMIFR1 bit must be set before the EOD symbol is received or it remains cleared
and no IFR transmit attempts are made. The TMIFR1 bit is cleared after the CRC byte and EOD are
transmitted, if an error is detected on the bus, if a loss of arbitration occurs during the IFR transmission or
if a transmitter underrun occurs when the user fails to service the TDRE interrupt in a timely manner. If a
loss of arbitration occurs while the Type 3 IFR is being transmitted, transmission halts immediately and
the loss of arbitration is indicated in the BDLC_DLCBSVR register.
6.4.7.5
The Transmit Multi-Byte IFR 0 (TMIFR0) bit is used to transmit an SAE J1850 Type 3 IFR without a CRC
byte appended. If this bit is set after the user has loaded the first byte of a multi-byte IFR into the BDLC
Data Register, the BDLC module begins transmitting that byte, preceded by the appropriate Normalization
Bit, onto the SAE J1850 bus. After this happens, a TDRE interrupt occurs, indicating to the user that the
next IFR byte should be loaded into the BDLC Data Register. When the last byte to be transmitted is
written to the BDLC Data Register, the user sets the TEOD bit. This causes an EOD symbol to be
transmitted following the last IFR byte.
As with the TSIFR and TMIFR1 bits, the TMIFR0 bit must be set before the EOD symbol is received or
it remains cleared and no IFR transmit attempts are made. The TMIFR0 bit is cleared after the CRC byte
and EOD are transmitted, if an error is detected on the bus, if a loss of arbitration occurs during the IFR
6-48
Transmit Single Byte IFR
Transmit Multi-Byte IFR 1
Transmit Multi-Byte IFR 0
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor