MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 226

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
Direct Memory Access (DMA)
9-6
0x15A0–0x115BC TCD45—Transfer Control Descriptors Channel 45
0x117C0–0x171DC TCD62—Transfer Control Descriptors Channel 62
0x1800–0x3FFF Reserved
0x1480–0x149C TCD36—Transfer Control Descriptors Channel 36
0x1500–0x153C TCD40—Transfer Control Descriptors Channel 40
0x1520–0x153C TCD41—Transfer Control Descriptors Channel 41
0x1540–0x155C TCD42—Transfer Control Descriptors Channel 42
0x1560–0x157C TCD43—Transfer Control Descriptors Channel 43
0x1580–0x159C TCD44—Transfer Control Descriptors Channel 44
0x1600–0x161C TCD48—Transfer Control Descriptors Channel 48
0x1620–0x163C TCD49—Transfer Control Descriptors Channel 49
0x1640–0x165C TCD50—Transfer Control Descriptors Channel 50
0x1660–0x167C TCD51—Transfer Control Descriptors Channel 51
0x1680–0x169C TCD52—Transfer Control Descriptors Channel 52
0x1700–0x173C TCD56—Transfer Control Descriptors Channel 56
0x1740–0x175C TCD58—Transfer Control Descriptors Channel 58
0x1760–0x177C TCD59—Transfer Control Descriptors Channel 59
0x1780–0x179C TCD60—Transfer Control Descriptors Channel 60
0x14A0–0x14BC TCD37—Transfer Control Descriptors Channel 37
0x14C0–0x14DC TCD38—Transfer Control Descriptors Channel 38
0x15C0–0x15DC TCD46—Transfer Control Descriptors Channel 46
0x16A0–0x16BC TCD53—Transfer Control Descriptors Channel 53
0x16C0–0x16DC TCD54—Transfer Control Descriptors Channel 54
0x1720–0x1713C TCD57—Transfer Control Descriptors Channel 57
0x17A0–0x17BC TCD61—Transfer Control Descriptors Channel 61
(0xFF41_4000)
0x15E0–0x14FC TCD39—Transfer Control Descriptors Channel 39
0x15E0–0x15FC TCD47—Transfer Control Descriptors Channel 47
0x16E0–0x16FC TCD55—Transfer Control Descriptors Channel 55
0x17E0–0x17FC TCD63—Transfer Control Descriptors Channel 63
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
DMA_BASE
Offset from
1
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-1. DMA memory map (continued)
Register
Chapter 2, “System Configuration and Memory
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
Reset Value
Freescale Semiconductor
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
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