MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 549

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.2.1.1.3
21.2.1.1.4
Freescale Semiconductor
Address: Base + 0x020
Address: Base + 0x024
Reset
Reset
Reset
Reset
Field
Field
ME
RO
W
W
W
W
IE
R
R
R
R
16
16
0
0
0
0
0
0
0
0
0
0
Chip Select Control (LPC_CSC) Register
Chip Select Status (LPC_CSS) Register
Read only bit. If the bit is high, the device is treated as a read-only device. An attempted write access can
results in an interrupt (as dictated by the Chip Select Control (LPC_CSC) Register IE bit). In any case, no
transaction is presented to the device.
Interrupt enable bit. An interrupt can be generated if a write is initiated to a read-only define CS; a read is
initiated to a write-only defined CS; an SCLPC state machine finishes transfer (normal or abort); or an SCLPC
FIFO detects FIFO errors (underrun or overrun).
Master enable bit that is a global module enable bit. If this bit is low, register access can continue to occur, but
no external transactions are accepted. However, ME does not affect boot ROM operation on CS[0]. For
software to disable CS[0], it must write 0 to the chip select boot ROM configuration register enable bit (CE).
17
17
0
0
0
0
0
0
0
0
1
1
WOerr ROerr
w1c
18
18
0
0
0
0
0
0
0
2
2
Figure 21-4. Chip Select Control (LPC_CSC) Register
Table 21-4. LPC_CSnC field descriptions (continued)
Figure 21-5. Chip Select Status (LPC_CSS) Register
w1c
19
19
0
0
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
IE
20
20
4
0
0
0
4
0
0
0
0
Table 21-5. CSC field descriptions
21
21
0
0
0
0
0
0
0
5
5
CSxerr
22
22
0
0
0
0
0
0
0
6
6
ME
23
23
0
0
0
0
0
0
7
7
Description
Description
24
24
8
0
0
0
0
8
0
0
0
0
25
25
9
0
0
0
0
9
0
0
0
0
10
26
10
26
0
0
0
0
0
0
0
0
11
27
11
27
0
0
0
0
0
0
0
0
LocalPlus Bus Controller (LPC)
12
28
12
28
0
0
0
0
0
0
0
0
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
0
0
0
15
31
15
31
21-9
0
0
0
0
0
0
0
0