MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 569

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In Non-Muxed mode the address and data are driven simultaneously on the external AD/AX bus. A single
dedicated R/W pin is driven to indicate read or write. An individually dedicated CS pin is driven low while
an external access is active.
Wait states are programmable and simply select how many LPC clocks the CS pin remain asserted.
Separate values are available for read cycles versus write cycles. These values can be combined to create
extremely long (up to 16 bits) cycles. Byte lane swapping is separately programmable between reads
versus writes and can be used to perform endian conversions. The 24-bit data width is not supported.
Devices can be marked as read-only or write-only by setting a control bit in the appropriate LPC register.
Attempted accesses in violation of this setting are prevented. Each CS pin can be individually
enabled/disabled and the entire LPC module has a master enable bit. No software reset bit is provided or
needed.
The non-muxed mode requires no external logic for interfacing to simple devices such as flash ROM,
EEPROM or SRAM. It is faster than the muxed mode because data and address are provided in a single
tenure.
Freescale Semiconductor
DATA (wr)
LPC_CLK
DATA (rd)
TSIZ[1:0]
Note:
ADDR
CS[x]
This diagram represents a holdcycle setting of 1.
This diagram represents a deadcycle setting of 2.
This diagram represents a wait state setting of 2.
R/W
Figure 21-28. Timing Diagram—Non-Muxed Mode with Different Timing Settings
OE
TS
MPC5125 Microcontroller Reference Manual, Rev. 2
Valid Write Data
Valid Address
Valid Read Data
LocalPlus Bus Controller (LPC)
21-29