MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 331

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
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output used by the controller to clock the read data. If the DRAM controller produces the read
strobes at an incorrect time, or produces not enough or too many read strobes, the DRAM controller
may detect some error conditions because they result in an overflow or underflow of the FIFO that
keeps track of the number of outstanding DQS pulses. These bits do not detect timing configuration
errors. Underflows and overflows signaled by the read FIFO point to following possible error
sources:
— Incorrect configuration of the DRAM. Burst length set incorrectly
— Incorrect configuration of the DRAM controller.
— Problems with the electrical connections between the DRAM controller and the DRAM
It contains a bypass path to send commands to the DRAM. This is because the DRAM controller
contains no logic to take care of DRAM initialization, programming the mode registers, or putting
the DRAM into or out of the sleep and standby modes like self-refresh. Essentially, these functions
are made available over the peripheral bus. To program the mode registers, the DRAM controller
needs to be put in a bypass mode, where incoming requests are not serviced. In this bypass mode,
commands are sent from the peripheral interface directly to the DRAM to program the mode
registers or to put the DRAM into or out of sleep mode.
During bypass mode, all reads and writes are blocked. Refresh keeps running, but can be separately
disabled.
– Incorrect RDLY
– Incorrect HALF_DQS_DLY
– Incorrect QUART_DQS_DLY
– Incorrect DRAM timing parameters or mis-match between various settings.
MPC5125 Microcontroller Reference Manual, Rev. 2
DRAM Controller
11-23