MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 509

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.3.1.4
The I
are software clearable by writing a 0. Writing a 1 to the AL, AKF, and IF bits I2C does nothing. To avoid
clearing these three flags unintentionally, force a cleared bit to 0 and set a non-cleared bit to 1. For
example, to clear the AL bit, only the AL bit must be set to 0 (AL = 0). The other two flags should be equal
to 1 (AKF = 1, IF = 1).
Freescale Semiconductor
TXAK
RSTA
Field
STA
IEN
TX
2
C status register (I2C_MSRn) is read-only with the exception of the AL, AKF, and IF bits, which
I
0 Interrupts from I
1 Interrupts from I
Master/Slave Mode Select. Bit clears on reset. When bit changes from 0 to 1, a START signal is generated on the
bus and master mode is selected.
When bit changes from 1 to 0, a STOP signal is generated and operation mode changes from master to slave.
STA is cleared without generating a STOP signal when the master loses arbitration.
0 Slave Mode
1 Master Mode
Transmit/Receive Mode Select. Bit selects master/slave transfer direction. When addressed as slave, software
should set according to status register SRW bit.
When in master mode, bit should be set according to type of transfer required.
For address cycles, bit is always high.
0 Receive
1 Transmit
Transmit Acknowledge Enable. Bit specifies value driven to SDA during acknowledge cycles for master and slave
receivers. Values are used only when I
0 Acknowledge signal is sent to bus at 9th clock bit after receiving 1Byte of data.
1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)
Repeat Start. Writing 1 to this bit generates a repeated START condition on the bus, provided it is the current bus
master. Bit is always read low.
If the bus is owned by another master, attempting a repeated start at the wrong time results in loss of arbitration.
1 Generate repeat start cycle
2
C Interrupt Enable
I
2
C Status Register (I2C_MSRn)
2
2
Table 19-7. I2C_MCRn field descriptions (continued)
C module are disabled. This does not clear currently pending interrupt conditions.
C module are enabled. An I
MPC5125 Microcontroller Reference Manual, Rev. 2
2
C is a receiver, not a transmitter.
2
C interrupt occurs, provided the status register IF bit is also set.
Description
Inter-Integrated Circuit (I
19-17
2
C)