MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 688

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25-10
TxEMP/URERR UART. Transmitter Empty.
FE/PHYERR
CDE/DEOF
RB/EOF
ORERR
Field
Error
PE
UART. Received Break. Detects breaks originating in middle of received character. Such a break must
persist until the end of next detected character time.
0 No break received.
1 An all-0 character of the programmed length was received without a stop bit.Only a single FIFO position
Other Modes. Reserved.
UART. Framing Error. Not used (always 0) in codec mode.
0 No framing error occurred.
1 No stop bit detected when corresponding FIFO data character received. Stop bit-check occurs in middle
Other Modes. Reserved.
UART. Parity Error. PE is not used (always 0) in codec mode.
0 No parity error occurred.
1 If MR1[PM]equals 0x (with parity or force parity), corresponding FIFO character was received with
Other Modes. Reserved.
Overrun Error. Indicates whether an overrun occurs. For purposes of overrun, FIFO full means all FIFO
space is occupied; the Rx FIFO threshold is irrelevant to overrun.
0 No overrun occurred.
1 One or more characters in Rx data stream were lost. ORERR sets on receipt of a new character when
0 Tx buffer not completely empty. Either a character is being shifted out, or Tx is disabled. Tx is
1 Tx has underrun (both the Tx holding register and Tx shift registers are empty). This bit sets after
Other Modes. Underrun Error.
0 No error.
1 Underrun error occurred, which means the number of Tx FIFO bytes is 0, the Tx shift register is empty,
UART. DCD Status.
0 The DCD input is negated while receiving data.
1 No error.
Other Modes. Reserved.
Error Status Detect.
0 No error.
1 The PSC controller detected an error state. This error is a combination of the error bits: RB, FE, PE,
Other Modes. Reserved.
is occupied when a break is received. Further entries to FIFO are inhibited until RxD returns to high state
for at least one-half bit-time, which equals two successive PSC clock edges.
of first stop bit position.
incorrect parity. If MR1[PM] equals 11 (multidrop), PE stores received A/D bit.
FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this
occurs, the character in the Rx shift register and its break detect, framing error status, and parity error, if
any, are lost. ORERR is cleared by the RESET ERROR STATUS command in CR.
enabled/disabled by programming CR [TC].
transmission of the last stop bit of a character, if there are no characters in the Tx holding register awaiting
transmission.
and a FrameSync occurs. In other words, the time has come to transmit a new sample, but no sample is
available in the Tx shift register. Unlike UART mode, TxEMP high indicates an error condition similar to
the overrun condition (ORERR = 1). It is now cleared the same way as ORERR by a RESET ERROR
STATUS command in the CR and not by a reset Tx command in the CR.
URERR, ORERR from this register and RX and RX FIFO bit from the TFSTAT and RFSTAT register.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-8. SR field descriptions
Description
Freescale Semiconductor