MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 359

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The RAM is the central point of all data flow in the Fast Ethernet controller. The RAM is divided into
transmit and receive FIFOs and the boundary is programmable (ETH_R_FSTART register). User data
flows to/from the DMA unit from/to the receive/transmit FIFOs. Transmit data flows from the transmit
FIFO into the transmit block and receive data flows from the receive block into the receive FIFO.
The bus controller decides which block is the tbus master on each clock. All of the blocks receive their
control information from the tbus and, for the most part, provide status information over this same bus.
The user controls FEC by writing into control registers located in each block. The CSR (control and status
register) block provides global control (e.g., Ethernet reset and enable, mode control) and interrupt
managing registers.
The MII block provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of the MDC (clock) and MDIO (bidirectional data) lines
of the MII interface.
The FEC DMA block (not to be confused with DMA controller) provides multiple channels allowing
transmit data, transmit descriptor, receive data and receive descriptor accesses to run independently.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from
microcode). Internal to these blocks are clock domain boundaries between the system clock and the
network clocks.
The MIB block maintains counters for a variety of network events and statistics. It is not necessary for
operation of the FEC but provides valuable counters for network management. The counters supported are
the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3 counters.
14.1.2
The fast Ethernet controller (FEC) incorporates several features/design goals important to its market:
Freescale Semiconductor
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Support for different Ethernet physical interfaces:
— 100 Mbit/s IEEE 802.3 MII
— 10 Mbit/s IEEE 802.3 MII
— 100 Mbit/s reduced media independent interface (RMII)
— 10 Mbit/s reduced media independent interface (RMII)
— 10 Mbit/s 7-wire interface (industry standard)
IEEE 802.3 full-duplex flow control
Features
DMA references in this section refer to the FEC’s DMA engine. This DMA
engine transfers FEC data only and is not related to the DMA controller in
MPC5125.
The FIFO is used by FEC itself and can only be accessed by the DMA. You
can configure the transmit/receive FIFO boundary (ETH_R_FSTART
register).
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
Fast Ethernet Controller (FEC)
14-3