MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 996

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.8.6.2
As discussed in
treatment by the DCD. A setup transfer does not use a dTD, but stores the incoming data from a setup
packet in an 8-byte buffer within the dQH instead.
Upon receiving notification of the setup packet, DCD should manage setup transfer as demonstrated here:
32-168
•
•
•
•
•
1. Copy setup buffer contents from dQH - RX to software buffer.
2. Acknowledge setup backup by writing a 1 to the corresponding bit in the
3. Check for pending data or status dTDs from previous control transfers and flush if any exist as
4. Decode setup packet and prepare data phase [optional] and status phase transfer as required by the
Write the wMaxPacketSize field as required by the USB Chapter 9 or application specific protocol.
Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO endpoints, set the
multiplier to 1,2, or 3 as required bandwidth with the USB Chapter 9 protocol.
Write the next dTD Terminate bit field to 1.
Write the active bit in the status field to 0.
Write the halt bit in the status field to 0.
USB_ENDPTSETUPSTAT register.
discussed in section flushing/de-priming an endpoint.
USB Chapter 9 or application specific protocol.
Operational Model For Setup Transfers
In FS mode, the multiplier field can only be 1 for ISO endpoints.
The DCD must only modify dQH if the associated endpoint is not primed
and there are no outstanding dTD's.
The acknowledge must occur before continuing to process the setup packet.
After the acknowledge has occurred, the DCD must not attempt to access
the setup buffer in the dQH - RX. Only the local software copy should be
examined.
It is possible for the device controller to receive setup packets before
previous control transfers complete. Existing control packets in progress
must be flushed and the new control packet completed.
Section 32.8.5.2, “Control Endpoint Operation Model,”
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
NOTE
NOTE
NOTE
setup transfer requires special
Freescale Semiconductor