MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 794

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28.3.2.14 SDHC Data Buffer Access (SDHC_BUFFER_ACCESS) Register
The SDHC uses two 64-byte data buffers in an alternating manner to transfer data by the DMA and the SD
card simultaneously to maximize throughput between the two clock domains (the IP peripheral clock,
SDHC_CLK, and the host clock, CLK_20M). These buffers are temporary storage for data transferred
between the host system and the card and vice versa. Read or write data to the buffers through this buffer
access register. Refer to
In the read operation, the SDHC stores data received from the card into the buffer. Move the data out of
the buffer when the buffer is full.
In the write operation, the SDHC fetches data from the buffer and transfers it to the card. Access the data
buffer through the SDHC data buffer access register. Move data into the buffer when the buffer is empty.
Figure 28-15
28-22
Address: Base + 0x34
RESPONSE_
CONTENT
Reset
Reset
Field
W
W
R
R
16
0
0
0
0
shows the SDHC_BUFFER_ACCESS register and
Response Content FIFO access register. A FIFO in the SDHC stores the command response received from
the card. Every time the Host sends a command to a card, the current contents stored in the FIFO are cleared
and a new response argument is stored into the response FIFO.
According to the SD card spec, command response size can be 48-bit or 136-bit (R2 response). Refer to the
SD Memory Card Specification for more detailed information about the command response format. The
response FIFO is 8 × 16 bits (128 bits). For a 48-bit response, only 48 bits of the FIFO have valid contents
and software must perform three reads to this response FIFO access register to retrieve the entire 48-bit
response content. For a 136-bit R2, response (response for CID[127:0] or CSD[127:0] register), only the
contents of the 128-bit CID and CSD register are stored in the response FIFO. This first byte of the R2
response is not stored in the response FIFO. Retrieve the CIS/CSD register from the response FIFO through
eight accesses to the FIFO access register. The CRC bit in the response is not stored in the response FIFO.
This response FIFO is read only.
17
0
0
0
Figure 28-14. SDHC Response FIFO Access (SDHC_RES_FIFO) Register
1
18
0
0
0
2
Section 28.4.1, “Data Buffers,”
19
Table 28-17. SDHC_RES_FIFO field descriptions
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
21
0
0
0
5
RESPONSE_CONTENT
22
0
0
0
6
23
0
0
0
7
Description
for more information about the data buffers.
24
8
0
0
0
25
Table 28-15
9
0
0
0
10
26
0
0
0
11
27
0
0
0
describes the bit fields.
12
28
0
0
0
Freescale Semiconductor
Access: User read-only
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0