MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 995

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.8.6
The device queue head (dQH) points to the linked list of transfer tasks, each depicted by the device transfer
descriptor (dTD). An area of memory pointed to by USB_ENDPOINTLISTADDR contains a group of all
dQH's in a sequential list as shown in
endpoints (OUT/SETUP) and the odd elements are for transmit endpoints (IN/INTERRUPT). Device
transfer descriptors are linked head to tail starting at the queue head and ending at a terminate bit. After
the dTD has been retired, it is no longer part of the linked list from the queue head. Therefore, software is
required to track all transfer descriptors because pointers no longer exist within the queue head once the
dTD is retired (see section Software Link Pointers).
In addition to the current and next pointers and the dTD overlay examined in the section on operational
model for packet transfers, dQH also contains the following parameters for the associated endpoint:
multiplier, maximum packet length, interrupt on setup. The complete initialization of the dQH including
these fields is demonstrated in the next section.
32.8.6.1
One pair of device queue heads must be initialized for each active endpoint. To initialize a device queue
head:
Freescale Semiconductor
USB_ENDPOINTLISTADDR
Managing Queue Heads
Queue Head Initialization
1
2
Invalid
Zero Length Packet
Force Bit Stuff Error
Ping
Table 32-96. Isochronous Endpoint Bus Response Matrix (continued)
Ignore
Ignore
Stall
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 32-75. Endpoint Queue Head Diagram
Endpoint Queue Heads
(as many as 32 elements)
Endpoint QH0 - Out
Endpoint QH1 - Out
Figure
Endpoint QH0 - In
Not Primed
Ignore
Ignore
32-75. The even elements in the list of dQH's are receive
Primed
Ignore
Ignore
Descriptors
Underflow
Endpoint
Transfer
Ignore
Ignore
Universal Serial Bus Interface with On-The-Go
Transfer Buffer
Transfer Buffer
Pointer
Pointer
Overflow
Ignore
Ignore
Transfer
Transfer
Transfer
Transfer
Buffer
Buffer
Buffer
Buffer
32-167