MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 1002

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
(USB_USBSTS) Register,”
more information.
32.8.10.4 Embedded Design
This is an embedded USB host controller as defined by the EHCI specification and does not implement
the PCI configuration registers.
32.8.10.4.1 Frame Adjust Register
Because the optional PCI configuration registers are not included in this implementation, there is no
corresponding bit level timing adjustments like those provided by the frame adjust register in the PCI
configuration registers. Starts of microframes are timed precisely to 125 µsec using the transceiver clock
as a reference clock.
32.8.10.5 Miscellaneous Variations from EHCI
32.8.10.5.1 Programmable Physical Interface Behavior
The modules support multiple physical interfaces which can operate in different modes when the module
is configured with the software programmable physical interface modes. The control bits for selecting the
PHY operating mode have been added to the USB_PORTSCn register providing a capability defined by
EHCI specification.
32.8.10.5.2 Discovery
The port connect methods specified by EHCI require setting the port reset bit in the register for a duration
of 10 msec. Due to the complexity required to support the attachment of devices that are not high speed,
counters are already present in the design that can count the 10 msec reset pulse to alleviate the
requirement of the software to measure this duration. Therefore, the basic connection is then summarized
as the following:
After the port change interrupt indicates a port is enabled, EHCI stack should determine the port speed.
Unlike EHCI implementation, which re-assigns the port owner for any device that does not connect at
high-speed, this host controller supports direct attach of non-HS devices. Therefore, the following
differences are important regarding port speed detection:
32-174
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•
•
•
•
[Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device
has attached.
Software shall write a 1 to the reset bit of the device.
Software shall write a 0 to the reset bit of the device after 10 msec.
— This step (necessary in a standard EHCI design) may be omitted with this implementation.
[Port Change Interrupt] Port enable change occurs to notify the host controller the device is now
operational, and at this point, the port speed has been determined.
Port owner is read-only and always reads 0.
Should the EHCI host controller driver attempt to write a 0 to the reset bit while a reset is in
progress, the write is ignored and the reset continues until completion.
and
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 32.2.4.3, “USB Interrupt Enable Register (USB_USBINTR),”
Freescale Semiconductor
for