MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 876

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.2.4.23 Endpoint Status (USB_ENDPTSTATUS) Register
The Endpoint Status (USB_ENDPTSTATUS) register is not defined in the EHCI specification. This
register is used only by the OTG module in device mode.
32-48
Address: Base + 0x1B4
Address: Base + 0x1B8
Reset
Reset
Reset
Reset
FERB
FETB
Field
W
W
W
W
R
R
R
R
16
16
0
0
0
0
0
0
0
0
0
0
Flush Endpoint Transmit Buffer. Writing a 1 to a bit(s) in this register causes the associated endpoint(s) to clear
any primed buffers. If a packet is in progress for one of the associated endpoints, that transfer continues until
completion. Hardware clears this register after the endpoint flush operation is successful.
FETB[3]—Endpoint #3
FETB[2]—Endpoint #2
FETB[1]—Endpoint #1
FETB[0]—Endpoint #0
Flush Endpoint Receive Buffer. Writing a 1 to a bit(s) causes the associated endpoint(s) to clear any primed
buffers. If a packet is in progress for one of the associated endpoints, that transfer continues until completion.
Hardware clears this register after the endpoint flush operation is successful.
FERB[3]—Endpoint #3
FERB[2]—Endpoint #2
FERB[1]—Endpoint #1
FERB[0]—Endpoint #0
17
17
0
0
0
0
0
0
0
0
1
1
Figure 32-37. Endpoint Status (USB_ENDPTSTATUS) Register
18
18
0
0
0
0
Figure 32-36. Endpoint Flush (USB_ENDPTFLUSH) Register
0
0
0
0
2
2
Table 32-37. USB_ENDPTFLUSH field descriptions
19
19
0
0
0
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
4
0
0
0
0
4
0
0
0
0
21
21
0
0
0
0
0
0
0
0
5
5
22
22
0
0
0
0
0
0
0
0
6
6
23
23
0
0
0
0
0
0
0
0
7
7
Description
24
24
8
0
0
0
0
8
0
0
0
0
25
25
9
0
0
0
0
9
0
0
0
0
10
26
10
26
0
0
0
0
0
0
0
0
11
27
11
27
0
0
0
0
0
0
0
0
12
28
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read-only
13
29
13
29
0
0
0
0
ERBR
FERB
ETBR
FETB
14
30
14
30
0
0
0
0
15
31
15
31
0
0
0
0