MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 602

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
22.3.2.16 MSCAN Identifier Acceptance Register (CANIDAR0–CANIDAR7)
On reception, each message is written into the background receive buffer. The Power Architecture is
signaled to read the message only if it passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message is overwritten by the next message (dropped).
22-24
TXERR[7:0]
Address: Base + 0x1D
Address: Base + 0x20 (CANIDAR0)
AC[7:0]
Reset
Reset
Field
Field
W
W
R
R
Base + 0x21 (CANIDAR1)
Base + 0x24 (CANIDAR2)
Base + 0x25 (CANIDAR3)
TXERR7
Figure 22-18. MSCAN Identifier Acceptance Registers (CANIDAR0–CANIDAR7)
AC7
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value.
This register reflects the status of the MSCAN receive error counter.
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Acceptance Code Bits. AC[7:0] comprises a user defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this
comparison is masked with the corresponding identifier mask register.
0
0
0
0
Figure 22-17. MSCAN Transmit Error Counter Register (CANTXERR)
TXERR6
Table 22-19. CANIDAR0–CANIDAR7 field descriptions
AC6
1
0
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 22-18. CANTXERR field descriptions
TXERR5
AC5
0
0
2
2
Base + 0x30 (CANIDAR4)
Base + 0x31 (CANIDAR5)
Base + 0x34 (CANIDAR6)
Base + 0x35 (CANIDAR7)
TXERR4
NOTE
AC4
0
0
3
3
Description
Description
TXERR3
AC3
0
0
4
4
TXERR2
AC2
0
0
5
5
TXERR1
Freescale Semiconductor
Access: User read/write
Access: User read-only
AC1
0
0
6
6
TXERR0
AC0
0
0
7
7