MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 593

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.3.2.5
A flag can only be cleared when the condition that caused the setting is no longer valid and can only be
cleared by software (writing a 1 to the corresponding bit position). Every flag has an associated interrupt
enable bit in the CANRIER register.
The CANRFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and
INITAK = 1). This register is writable again as soon as the initialization mode is left (INITRQ = 0 and
INITAK = 0).
Read: Anytime
Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags, which are
read-only; write of 1 clears flag; write of 0 ignored
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
Freescale Semiconductor
Address: Base + 0x08
WUPIF
CSCIF
Reset
Field
W
R
WUPIF
MSCAN Receiver Flag Register (CANRFLG)
w1c
The CANRFLG register is held in the reset state
mode is active (INITRQ = 1 and INITAK = 1). This register is writable
again as soon as the initialization mode is exited (INITRQ = 0 and
INITAK = 0).
Wake-Up Interrupt Flag. If the MSCAN detects CAN bus activity while in sleep mode (see
“MSCAN Sleep
(CANCTL0)”), the module sets WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.
0 No wake-up activity observed while in Sleep Mode.
1 MSCAN detected activity on the bus and requested wake-up.
CAN Status Change Interrupt Flag. This flag is set when the MSCAN changes its current CAN bus status due
to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit
(RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the
system on the actual CAN bus status (see
(CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking
interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no
CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is
asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status
until the current CSCIF interrupt is cleared again.
0
1
0
0
No change in CAN bus status occurred since last interrupt
MSCAN changed current CAN bus status
Figure 22-7. MSCAN Receiver Flag Register (CANRFLG)
CSCIF
w1c
1
0
Mode,”) and WUPE = 1 in CANTCTL0 (see
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 22-8. CANRFLG field descriptions
0
2
RSTAT[1:0]
NOTE
Section 22.3.2.6, “MSCAN Receiver Interrupt Enable Register
0
3
Description
0
1
4
Section 22.3.2.1, “MSCAN Control 0 Register
when the initialization
TSTAT[1:0]
0
5
OVRIF
Access: User read/write
w1c
0
6
Section 22.4.8.1,
RXFIF
w1c
0
7
MSCAN
22-15