MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 84

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Signal Descriptions
3.2
When a system reset is recognized (PORESET or HRESET are asserted), the MPC5125 aborts all current
internal and external transactions, and it releases all bidirectional I/O signals to a high-impedance state.
See
During reset, the MPC5125 ignores most input signals (except for reset configuration signals
and drives most of the output-only signals to an inactive state.
output-only signals if boot from LPC or not boot from LPC.
3-32
Chapter 4, “Reset,”
EMB_AX[2]
EMB_AX[1]
EMB_AX[0]
LPC_AX[3]
I2C2_SDA
NFC_CE0
DIU_LD00
DIU_LD01
DIU_LD08
DIU_LD09
DIU_LD16
DIU_LD17
I2C2_SCL
I2C1_SCL
LPC_R/W
LPC_ACK
LPC_CS0
Interface
MBA[2:0]
MA[15:0]
LPC_OE
MRAS
MCAS
MCKE
MODT
MWE
Signal States During Reset
MCS
MCK
MCK
Table 3-2. Signal States During System Reset (case boot from LPC)
for a complete description of the reset functionality.
DDR bank select
DDR address
DDR write enable
DDR row address strobe
DDR column address strobe
DDR chip select
DDR clock enable
DDR differential clock
DDR differential clock
DRAM On-Die Termination
LocalPlus output enable
LocalPlus read/write bar
External Memory Bus address extension 3/LocalPlus
Address latch
External Memory Bus address extension 2/LocalPlus
Address latch
External Memory Bus address extension 1/LocalPlus
Address latch
External Memory Bus address extension 0/LocalPlus
Address latch
LPC Acknowledge
LPC Chip Select 0
NFC Chip Enable 0
CAN3_RX
CAN3_TX
CAN4_RX
CAN4_TX
I2C3_SCL
I2C3_SDA
I2C2_SCL
I2C2_SDA
I2C1_SCL
MPC5125 Microcontroller Reference Manual, Rev. 2
Signal
Table
3-2, and
Table 3-3
State During Reset
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Pullup resistor
Freescale Semiconductor
shows states of the
16’h8000
All 0
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Table
3-2)