MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 334

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multi-port DRAM Controller Priority Manager
12.1.1
12.2
The following masters are connected to five buses.
12.3
12.3.1
12-2
PRIOMAN_BASE
(0xFF40_9000)
Offset from
•
•
•
•
•
•
•
0x008C
0x009C
0x0080
0x0084
0x0088
0x0090
0x0094
0x0098
Dynamic priority calculation based on ACKing history
— Fully programmable using look-up table
— Fairness guaranteed by reducing priority of channels that receive a lot of grants, and increasing
— Repeat transfer built into the DRAM controller. Priority manager can set the maximum repeat
Feed-through mode where DIU priority is controlled directly by the DIU
Bus 0: DIU
Bus 1: Power architecture e300
Bus 2: NFC
Bus 3: Reserved
Bus 4: USB, DMA, FEC
Bus Connections
Memory Map and Register Definition
– Can be configured for high or low latency and high or low bandwidth
– Separate control over average latency and average bandwidth
– Versatile so it can mimic the CSB arbitration schema
priority of channels that are denied the bus often
count by controlling when lowest priority occurs.
Features
Memory Map
1
Priority Manager Configuration 1 Register
(PRIOMAN_CONFIG1)
Priority Manager Configuration 2 Register
(PRIOMAN_CONFIG2)
High Priority Configuration Register (HIPRIO_CONFIG)
Look-Up Table 0 Main Upper (LUT_TABLE0_MAIN_UP)
Look-Up Table 1 Main Upper (LUT_TABLE1_MAIN_UP)
Look-Up Table 2 Main Upper (LUT_TABLE2_MAIN_UP)
Look-Up Table 3 Main Upper (LUT_TABLE3_MAIN_UP)
Look-Up Table 4 Main Upper (LUT_TABLE4_MAIN_UP)
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 12-1. PRIOMAN memory map
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
0x0000_UUUU
0x0000_00U1
Reset Value
0x0007_7777
0x1111_1222
0x1111_1222
0x1111_1222
0x1111_1222
0x1111_1222
Freescale Semiconductor
3
Section/Page
12.3.2.1/12-5
12.3.2.2/12-6
12.3.2.3/12-7
12.3.2.4/12-8
12.3.2.4/12-8
12.3.2.4/12-8
12.3.2.4/12-8
12.3.2.4/12-8