MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 673

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
24.3.1
This is the default power state of the e300 Power Architecture core. In this power mode, the core is fully
powered and the internal functional units are operating at the full-processor clock speed. If the dynamic
power management mode is enabled, functional units that are idle automatically enter a low-power state
without affecting performance, software execution, or external hardware.
24.3.2
In doze mode, all functional units of the core are disabled except the time base/decrementer registers and
the bus snooping logic.
This mode is entered by programming the doze bit (HID0[8] = 1) when MSR[POW] bit is set. The e300
core enters doze mode several processor clocks after these 2 bits are set.
An asynchronous interrupt, system management interrupt, decrementer interrupt, hard or soft reset, or
machine check input (mcp) brings the core into the full-power state. The core in doze mode maintains the
phase-locked loop (e300 PLL) in a full-power state and locked to the core external clock input
(CSB_CLK), so a transition to the full-power state takes only a few processor clock cycles.
The doze mode is an e300 core only low-power mode, the system stays in full-powered mode while the
core enters this mode. The core enters and exits doze mode without being controlled by the PMC.
24.3.3
The nap mode further reduces e300 power consumption by disabling bus snooping, leaving only the time
base register and the core PLL in a powered state. While the core enters nap mode, the system stays in
full-powered state.
Freescale Semiconductor
PRE_DIV copy mode with
HID0 is a register inside the e300 Power Architecture core.
MSR is a register inside the e300 Power Architecture core.
PMC_PMCCR register is described in section
PRE_DIV copy mode
DRAM in self-refresh
(not put DRAM to
self-refresh state)
Power mode
Full-Power Mode
Doze Mode
Nap Mode
Table 24-9. MPC5125 Power Modes – Sleep and Wake-Up Triggers (continued)
When the Power Architecture core is in debug mode, the PMC_PMCCR
register should be programmed to 0b00000. If the register is programmed to
any other value, unpredictable operation can result when the Power
Architecture core hits a breakpoint.
Events leading to entering this sleep mode
Set e300 SLEEP bit (HID0[10]
— POW bit in MSR
— PMC_PMCCR
Set e300 SLEEP bit (HID0[10]
— POW bit in MSR
— PMC_PMCCR
MPC5125 Microcontroller Reference Manual, Rev. 2
3
3
= 10000
= 10010
2
2
Section 24.2.2.1, “PMC Configuration Register (PMC_PMCCR).”
register is set
register is set
1
1
NOTE
= 1) while
= 1) while
Interrupt to e300 Power Architecture core
Reset
Machine check exception
Interrupt to e300 Power Architecture core
Reset
Machine check exception
Events leading to return to full power
Power Management Control Module (PMC)
24-9