MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 453

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.1.3.1
In core enable mode, all the MPC5125 internal interrupts and all machine check interrupts are routed
towards the IPIC unit and from the IPIC the interrupts are sent to the Power Architecture core.
18.1.3.2
In core disable mode all the MPC5125 internal interrupts are routed to and from the IPIC, but the IPIC will
not route any interrupt to the Power Architecture core.
18.2
18.2.1
The IPIC programmable register map occupies 256 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All IPIC registers are 32 bits wide and they are located on 32-bit address boundaries. Software can perform
byte, half-word or word accesses to any IPIC registers. All addresses used in this chapter are offsets from
the IPIC base, as defined in
Map).”
Table 18-1
Freescale Semiconductor
(0xFF40_0C00)
Offset from
IPIC_BASE
0x0C
0x1C
0x2C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
Memory Map/Register Definition
shows the memory map of the IPIC unit.
Register Summary
1
Core Enable Mode
Core Disable Mode
(IPIC_SIPRR_A)
System Internal Interrupt Group D Priority Register
System Global Interrupt Configuration Register (IPIC_SICFR)
System Global Interrupt Vector Register (IPIC_SIVCR)
System Internal Interrupt Pending Register (IPIC_SIPNR_H)
System Internal Interrupt Pending Register (IPIC_SIPNR_L)
System Internal Interrupt Group A Priority Register
System Internal Interrupt Group B Priority Register
(IPIC_SIPRR_B)
System Internal Interrupt Group C Priority Register
(IPIC_SIPRR_C)
(IPIC_SIPRR_D)
System Internal Interrupt Mask Register (IPIC_SIMSR_H)
System Internal Interrupt Mask Register (IPIC_SIMSR_L)
System Internal Interrupt Control Register (IPIC_SICNR)
System External Interrupt Pending Register (IPIC_SEPNR)
Chapter 2, “System Configuration and Memory Map (XLBMEN + Mem
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-1. IPIC Register Address Map
Register
Integrated Programmable Interrupt Controller (IPIC)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
2
0xU000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
0x0000_0000
0x0000_0000
0x0530_9770
0x0530_9770
0x0530_9770
0x0530_9770
0x0000_0000
0x0000_0000
3
18.2.1.10/18-22
18.2.1.3/18-11
18.2.1.3/18-11
18.2.1.4/18-14
18.2.1.5/18-15
18.2.1.6/18-16
18.2.1.7/18-17
18.2.1.8/18-18
18.2.1.8/18-18
18.2.1.9/18-21
Section/Page
18.2.1.1/18-6
18.2.1.2/18-8
18-5