MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 840

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.2.2
The capability registers specify the software limits, restrictions, and capabilities of the host/device
controller implementation. The EHCI specification defines most of these registers. Registers not defined
by the EHCI specification are noted in their descriptions.
32.2.2.1
This USB_CAPLENGTH register is an offset to add to the register base address to find the beginning of
the operational register space, the location of the USB_USBCMD register. The HCIVERSION entry
contains a BCD encoding of the EHCI revision number supported by this host controller. The
32-12
BURSTMODE Selects the following options for the burst signal of the Master Interface.
Field
Capability Registers
Capability Registers Length (USB_CAPLENGTH) / Host Controller
Interface Version (HCIVERSION) Register
000 INCR burst of unspecified length.
001 INCR4, non-multiple transfers of INCR4 is decomposed into singles.
010 INCR8, non-multiple transfers of INCR8, is decomposed into INCR4 or singles.
011 INCR16, non-multiple transfers of INCR16, is decomposed into INCR8, INCR4 or singles.
100 Reserved, do not use.
101 INCR4, non-multiple transfers of INCR4 is decomposed into smaller unspecified length bursts.
110 INCR8, non-multiple transfers of INCR8 is decomposed into smaller unspecified length bursts.
111 INCR16, non-multiple transfers of INCR16 is decomposed into smaller unspecified length bursts.
In all cases where the unspecified length burst is allowed, singles access may also occur, this is mostly true
when the transaction is not 32-bit aligned.
Two consecutive single accesses should not happen.
When an INCRx burst size is selected and the transfer is not multiple of the INCRx burst, the burst is
decomposed in the different ways. With BURSTMODE[2] = 1, the smaller bursts is unspecified length. with
BURSTMODE[2] = 0, the smaller bursts are smaller INCRx or singles. For example, if it were required at a
given time to transfer 22 words of information, for the following values of BURSTMODE the master sequences
are:
101 INCR4 + INCR4 + INCR4 + INCR4 + INCR4 + INCR unspec. length.
110 INCR8 + INCR8 + INCR4 + INCR unspec. length.
111 INCR16 + INCR4 + INCR unspec. length.
001 INCR4 + INCR4 + INCR4 + INCR4 + INCR4 + SINGLE + SINGLE.
010 INCR8 + INCR8 + INCR4 + SINGLE + SINGLE.
011 INCR16 + INCR4 + SINGLE + SINGLE.
When this field is different from zero, the values in the TXBURST/RXBURST bitfields in the USB_BURSTSIZE
register are ignored by the controller.
Internally the BURSTMODE is set to the value of the INCRx burst. Since this has a direct relation with the
burst sizes you must be careful with AHB burst selected. Although the TXBURST/RXBURST are bypassed,
this register can be written/read with no effect while the BURSTMODE field is non-zero.
Note: Setting the BURSTMODE value to 000 might cause bus allocation during BULK or ISO transfers.
Note: Changing this BURSTMODE field while a transaction is in progress yields undefined results. One
possible way to prevent undefined results is to clear the Run/Stop (RS) bit in the USB_USBCMD
register, after the HCHALTED is detected in USB_USBSTS.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-8. USB_SBUSCFG field descriptions
Description
Freescale Semiconductor