MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 408

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.6.12 Reception Errors
14-52
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— If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All
— The XFIFO_UN interrupt is asserted if enabled in the ETH_IMASK register
Carrier Sense Lost During Frame Transmission
— When this error occurs and no collision is detected in the frame, the FEC sets the CSL bit in
— No interrupt is generated as a result of this error
Retransmission Attempts Limit Expired
— When this error occurs, the FEC terminates transmission. All remaining buffers for that frame
— The COL_RETRY_LIM interrupt is asserted if enabled in the ETH_IMASK register
Late Collision
— When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC
— The LATE_COL interrupt is asserted if enabled in the ETH_IMASK register
Heartbeat
— Some transceivers have a self-test feature called heartbeat or signal quality error. To signify a
— If the HBC bit is set in the ETH_X_CNTRL register and the heartbeat condition is not detected
Overrun Error
— If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC
Non-Octet Error (Dribbling Bits)
remaining buffers for that frame are then flushed and closed. The UN bit is set in the
X_STATUS register. The FEC then continues to the next transmit buffer descriptor and begins
transmitting the next frame.
X_STATUS register. The frame is transmitted normally. No retries are performed as a result of
this error.
are then flushed and closed, and the RL bit is set in the X_STATUS register. The FEC then
continues to the next transmit buffer descriptor and begins transmitting the next frame.
terminates transmission. All remaining buffers for that frame are then flushed and closed, and
the LC bit is set in the X_STATUS register. The FEC then continues to the next transmit buffer
descriptor and begins transmitting the next frame.
good self-test, the transceiver indicates a collision to the FEC within 20 clocks after completion
of a frame transmitted by the Ethernet controller. This indication of a collision does not imply
a real collision error on the network, but is rather an indication that the transceiver seems to be
functioning properly. This is called the heartbeat condition.
by the FEC after a frame transmission, a heartbeat error occurs. When this happens, the FEC
closes the buffer, sets the HB bit in the X_STATUS register, and generates the HBERR interrupt
if it is enabled.
sets the OV bit in the receive status word. All subsequent data in the frame is discarded and
subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and
space becomes available. At this point, the receive frame/status word is written into the FIFO
with the OV bit set. This frame must be discarded by the driver.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor