MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 455

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Address: Base + 0x00
Reset
Reset
MPSB
MPSA
Field
IPSD
IPSC
IPSB
IPSA
HPI
W
W
R
R
16
0
0
0
0
0
Highest Priority Interrupt. Specifies the 7-bit unique interrupt number/vector
controller interrupt source advanced to the highest priority in the IPIC Priority table
modified dynamically.
Mixed interrupts Priority Scheme for group B. Selects the relative MIXB priority scheme. It cannot be changed
dynamically.
0 Grouped. The MIXBs are grouped by priority at the top of the table.
1 Spread. The MIXBs are spread by priority in the table.
Mixed interrupts Priority Scheme for group A. Selects the relative MIXA priority scheme. It cannot be changed
dynamically.
0 Grouped. The MIXAs are grouped by priority at the top of the table.
1 Spread. The MIXAs are spread by priority in the table.
Internal interrupts Priority Scheme for group D. Selects the relative SYSD priority scheme. It cannot be
changed dynamically.
0 Grouped. The SYSDs are grouped by priority at the top of the table.
1 Spread. The SYSDs are spread by priority in the table.
Internal interrupts Priority Scheme for group C. Selects the relative SYSC priority scheme. It cannot be
changed dynamically.
0 Grouped. The SYSCs are grouped by priority at the top of the table.
1 Spread. The SYSCs are spread by priority in the table.
Internal interrupts Priority Scheme for group B. Selects the relative SYSB priority scheme. It cannot be
changed dynamically.
0 Grouped. The SYSBs are grouped by priority at the top of the table.
1 Spread. The SYSBs are spread by priority in the table.
Internal Interrupts Priority Scheme for Group A. Selects the relative SYSA priority scheme. It cannot be
changed dynamically.
0 Grouped. The SYSAs are grouped by priority at the top of the table.
1 Spread. The SYSAs are spread by priority in the table.
Figure 18-2. System Global Interrupt Configuration Register (IPIC_SICFR)
17
0
0
0
1
18
0
0
0
2
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-2. IPIC_SICFR field descriptions
HPI
20
4
0
0
0
21
0
0
0
5
22
0
0
6
HPIT
23
0
0
7
Description
24
8
0
0
0
0
MPSB MPSA
Integrated Programmable Interrupt Controller (IPIC)
25
9
0
0
0
10
26
0
0
0
(Table
11
27
0
0
0
0
IPSD IPSC IPSB IPSA
18-4) of the single interrupt
12
28
(Table
0
0
0
Access: User read/write
18-28). HPI can be
13
29
0
0
0
14
30
0
0
0
15
31
18-7
0
0
0