MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 450

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
Figure
18-1shows the relationship of the various functional blocks and external signals of the MPC5125
to the IPIC unit.
The IPIC receives interrupt request signals from the sources external and internal to the integrated device
The unit selects the highest priority interrupt from all current interrupts and forwards it to the internal
processor core.
The IPIC also manages an internal non-maskable machine-check processor signal (mcp) and interrupt
generated by the off-chip interrupt sources (IRQ[1:0]).
The interrupt router of the IPIC monitors the outputs of the internal configuration registers. When the
priority is highest in one of the received interrupt signals, the IPIC sets the corresponding bit in one of the
interrupt pending registers (IPIC_SIPNRx or IPIC_SEPNR). If the interrupt is not masked, the IPIC asserts
the int, cint, or smi signal to indicate an interrupt request to the processor. When the processor is executing
the specific interrupt handler code, the processor must vectorize the external interrupt handler by explicitly
reading (in software) the corresponding interrupt vector register (IPIC_SIVCR, IPIC_SCVCR or
IPIC_SMVCR). In response to this read, the IPIC unit returns the vector (associated with the interrupt
source) to the interrupt handler routine. In addition, the handler can vectorize different branches of
interrupt handling.
MPC5125 Microcontroller Reference Manual, Rev. 2
18-2
Freescale Semiconductor