MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 246

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
Table 9-21
addressing, based on their individual addresses as shown in
Figure 9-22
9-26
TCDn Word
0
1
2
3
4
5
6
7
shows the addresses of the eight TCD words in TCD00. The other TCD channels repeat this
0x1000 + (32 × n) + 0x000C
0x1000 + (32 × n) + 0x001C
0x1000 + (32 × n) + 0x0000
0x1000 + (32 × n) + 0x0004
0x1000 + (32 × n) + 0x0008
0x1000 + (32 × n) + 0x0010
0x1000 + (32 × n) + 0x0014
0x1000 + (32 × n) + 0x0018
and
Table 9-22
DMA Offset
Table 9-21. Sample TCD Memory Structure for TCD00
define word 0 of the TCDn structure, the SADDR field.
MPC5125 Microcontroller Reference Manual, Rev. 2
TCD00 Word
Table 9-20. TCDn 32-bit Memory Structure
0
1
2
3
4
5
6
7
Current Major Iteration Count (CITER)
Last Destination Address Adjustment/Scatter Gather Address (DLAST_SGA)
(SMOD, SSIZE, DMOD, DSIZE)
Beginning Major Iteration Count
Transfer Attributes
(BITER)
Last Source Address Adjustment (SLAST)
Offset from DMA_BASE
Inner Minor Byte Count (NBYTES)
Destination Address (DADDR)
Table
Source Address (SADDR)
0x100C
0x101C
0x1000
0x1004
0x1008
0x1010
0x1014
0x1018
TCDn Field
9-1.
D_REQ, INT_HALF, INT_MAJ, START)
Signed Destination Address Offset
ACTIVE, MAJOR.E_LINK, E_SG,
(BWC, MAJOR.LINKCH, DONE,
Signed Source Address Offset
Channel Control/Status
Freescale Semiconductor
(SOFF)
(DOFF)