MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 992

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
USB_ENDPTPRIME bit is cleared, the transfer descriptor can be freed and the DCD must reinterpret the
setup packet.
Should a setup arrive after the data stage is primed, the device controller automatically clears the
USB_ENDPTSTATUS register to enforce data coherency with the setup packet.
Similar to the data phase, DCD must create a transfer descriptor (with byte length equal zero) and prime
the endpoint for the status phase. The DCD must also perform the same checks of the
USB_ENDPTSETUPSTAT as described above in the data phase.
Table 32-95
controller state.
32-164
1
2
3
Token Type
SYSERR — System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive.
Force Bit Stuff Error
NYET/ACK — NYET unless the transfer descriptor has packets remaining according to the USB variable length protocol
then ACK.
Invalid
Setup
Ping
Out
In
shows the device controller response to packets on a control endpoint according to the device
The MULT field in the dQH must be set to 00 for bulk, interrupt, and control
endpoints.
Error handling of data phase packets is the same as bulk packets described
previously.
The MULT field in the dQH must be set to 00 for bulk, interrupt, and control
endpoints.
Error handling of data phase packets is the same as bulk packets described
previously.
STALL
STALL
STALL
Ignore
Stall
ACK
Not Primed
Ignore
ACK
NAK
NAK
NAK
Table 32-95. Control Endpoint Bus Response Matrix
MPC5125 Microcontroller Reference Manual, Rev. 2
Receive + NYET/ACK
Transmit
Primed
Ignore
ACK
ACK
Endpoint State
NOTE
NOTE
NOTE
NOTE
3
Underflow
BS Error
Ignore
N/A
N/A
N/A
2
SYSERR
Overflow
Ignore
NAK
N/A
N/A
1
Enabled
BTO
BTO
BTO
BTO
BTO
Not
Freescale Semiconductor
Setup Lockout
Ignore
N/A
N/A
N/A
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