MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 240

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
9.2.1.11
The DMA Set START Bit (DMASSRT) register provides a simple memory-mapped mechanism to set the
START bit in the TCD of the given channel. The data value on a register write causes the START bit in
the corresponding Transfer Control Descriptor to be set. A data value of 64 to 127 (regardless of the
number of implemented channels) provides a global set function, forcing all START bits to be set. Reads
of this register return all 0s. See
9.2.1.12
The DMA Clear DONE Status (DMACDNE) register provides a simple memory-mapped mechanism to
clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE
bit in the corresponding Transfer Control Descriptor to be cleared. A data value of 64 to 127 (regardless
of the number of implemented channels) provides a global clear function, forcing all DONE bits to be
cleared. Reads of this register return all 0s. See
definition.
9-20
Address: Base + 0x001E
CERR[6:0]
SSRT[6:0]
Reset
Field
Field
W
R
DMA Set START Bit (DMASSRT)
DMA Clear DONE Status (DMACDNE)
Clear Error Indicator
0–63
64–127 Clears all the bits in the DMAERRH and DMAERRL registers.
Set START Bit (Channel Service Request)
0–63
64–127 Sets all TCD.START bits.
0
0
0
Clears the corresponding bit in the DMAERRH or DMAERRL register.
Sets the corresponding channel’s TCD.START bit.
Figure 9-13. DMA Set START Bit Register (DMASSRT)
1
0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 9-13
Table 9-13. DMACERR field descriptions
Table 9-14. DMASSRT field descriptions
0
0
2
and
Figure 9-14
Table 9-14
0
0
3
Description
Description
SSRT[6:0]
and
for the TCD.START bit definition.
0
0
4
Table 9-15
0
0
5
for the TCD.DONE bit
Freescale Semiconductor
Access: User read/write
0
0
6
0
0
7