MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 944

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.11.2.1 Split Transaction Scheduling Mechanisms for Interrupt
Full- and low-speed interrupt queue heads have an EPS field indicating full- or low-speed and have a
non-zero S-mask field. The host controller can detect this combination of parameters and assume the
endpoint is a periodic endpoint. Low- and full-speed interrupt queue heads require the use of the split
transaction protocol. The host controller sets the endpoint type (ET) field in the split token to indicate the
transaction is an interrupt. These transactions are managed through a transaction translator's periodic
pipeline. Software should not set these fields to indicate the queue head is an interrupt unless the queue
head is used in the periodic schedule.
System software manages the per/transaction translator periodic pipeline by budgeting and scheduling
exactly during which micro-frames the start-splits and complete-splits for each endpoint occur. The
characteristics of the transaction translator are such that the high-speed transaction protocol must execute
during explicit micro-frames or the data or response information in the pipeline is lost.
illustrates the general scheduling boundary conditions supported by the EHCI periodic schedule and queue
head data structure. The S and C
and complete splits (respectively).
The scheduling cases are:
32-116
•
Periodic Schedule
Case 1: The normal scheduling case is where the entire split transaction is completely bounded by
a frame (H-Frame in this case).
HS/FS/LS Bus
Micro-Frame
End of Frame
End of Frame
End of Frame
Micro-Frame
Normal Case
Case 2a:
Case 2b:
Case 2c:
Case 1:
Figure 32-64. Split Transaction and Interrupt Scheduling Boundary Conditions
B-Frame N–1
7
6
0
7
MPC5125 Microcontroller Reference Manual, Rev. 2
S
n
labels indicate micro-frames where software can schedule start-splits
1
0
2
1
C
0
3
2
H-Frame N
C
1
4
3
B-Frame N
C
S
2
5
4
S
6
5
C
S
0
7
6
C
C
0
1
0
7
C
C
C
0
1
2
Freescale Semiconductor
Figure 32-64
1
0
C
C
1
2
B-Frame N+1