MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 183

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This IFR type is typically used with Function-type messages, where the original transmitter may need to
know which nodes actually received the message. The basic difference between this type of IFR and the
Type 1 IFR is that the nodes that lose arbitration while attempting to transmit their node ID during a Type
2 IFR wait until the byte that wins arbitration is transmitted and then again attempt to transmit their node
ID onto the bus. The result is a series of node IDs, one from each receiver of the original message.
6.4.7.1.4
The last type of IFR defined by SAE J1850 is the Type 3 IFR. This IFR type consists of one or more bytes
from a single responder. This type of IFR is used to return data to the original transmitter within the
original message frame. This type of IFR may or may not have a CRC byte appended to it.
The Type 3 IFR is typically used with Function Read-type or Function Query-type messages, where the
original transmitter is requesting data from the intended receiver. The node requesting the data transmits
the initial portion of the message, and the intended receiver responds by transmitting the desired data in an
IFR. In most cases, the original message requiring a Type 3 IFR is addressed to one particular node, so no
arbitration should take place during the IFR portion of the message.
6.4.7.2
The BDLC module has three bits that are used to control the transmission of an In-Frame Response. These
bits, all located in BDLC Control Register 2, are TSIFR, TMIFR1, and TMIFR0. Each is used in
conjunction with the TEOD bit to transmit one of three IFR types defined in SAE J1850. What follows is
a brief description of each bit.
Because each of the bits used for transmitting an IFR with the BDLC module is used to transmit a
particular type of IFR, only one bit should be set by the CPU at a time. However, should more than one of
these bits get set at one time, a priority encoding scheme is used to determine which type of IFR is sent.
This scheme prevents unpredictable operation caused by conflicting signals to the BDLC module.
Table 6-23
the same time.
Freescale Semiconductor
illustrates which IFR bit is acted upon by the BDLC module should multiple IFR bits get set at
TSIFR
BDLC IFR Transmit Control Bits
0
1
0
0
IFR Type 3: Multiple Bytes from a Single Responder
As with transmitted messages, IFRs transmitted by the BDLC module are
also received by the BDLC module. For a description of how IFR bytes
received by the BDLC module should be handled, refer to
“Receiving An In-Frame Response (IFR).”
READ/WRITE
TMIFR1
—
0
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 6-23. IFR Control Bit Priority Encoding
TMIFR0
—
—
0
1
NOTE
TSIFR
0
1
0
0
ACTUAL
TMIFR1
Section 6.4.8,
0
0
1
0
Byte Data Link Controller (BDLC)
TMIFR0
0
0
0
1
6-47