MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 990

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
RX-dTD is complete when:
On the successful completion of the packet(s) described by the dTD, the active bit in the dTD is cleared
and the next pointer is followed when the terminate bit is clear. When the terminate bit is set, the USB
controller flushes the endpoint/direction and ceases operations for that endpoint/direction.
On the unsuccessful completion of a packet (see long packet above), the dQH is left pointing to the dTD
that was in error. To recover from this error condition, the DCD must properly re-initialize the dQH by
clearing the active bit and update the nextTD pointer before attempting to re-prime the endpoint.
There is no required interaction with the DCD for managing such errors.
32-162
•
•
•
•
All packets described dTD were successfully transmitted. Total bytes in dTD equal zero when this
occurs.
All packets described in dTD were successfully received. Total bytes in dTD equal zero when this
occurs.
A short packet (number of bytes < maximum packet length) was received. This is a successful
transfer completion; DCD must check total bytes in dTD to determine the number of bytes that are
remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes
received.
A long packet was received (number of bytes > maximum packet size) or (total bytes received >
total bytes specified). This is an error condition. The device controller discards the remaining
packet, and set the buffer error bit in the dTD. In addition, the endpoint is flushed and the USBERR
interrupt becomes active.
1
2
Invalid
Force Bit Stuff Error
NYET/ACK — NYET unless the transfer descriptor has packets remaining according to the USB variable
length protocol then ACK.
Setup
Ping
Out
In
All packet level errors, such as a missing handshake or CRC error, are
retried automatically by the device controller.
STALL
STALL
STALL
Ignore
Ignore
Stall
System error should never occur when the latency FIFOs are
correctly sized and the DCD is responsive.
Table 32-94. Interrupt/Bulk Endpoint Bus Response Matrix
Not Primed
MPC5125 Microcontroller Reference Manual, Rev. 2
Ignore
Ignore
NAK
NAK
NAK
Receive + NYET/ACK
NOTE
NOTE
Transmit
Primed
Ignore
Ignore
ACK
2
Underflow
BS Error
Ignore
N/A
N/A
N/A
1
Freescale Semiconductor
Overflow
Ignore
NAK
N/A
N/A
N/A