MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 916

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
packet size, etc.). It also uses the page select (PG) field to index the buffer pointer array, storing the
selected buffer pointer, and the next sequential buffer pointer. For example, if PG field is a 0, the host
controller stores Page 0 and Page 1.
The host controller constructs a physical data buffer address by concatenating the current buffer pointer
(as selected using the current transaction description's PG field) and the transaction description's
transaction offset field. The host controller uses the endpoint addressing information and I/O-bit to execute
a transaction to the appropriate endpoint. When the transaction is complete, the host controller clears the
active bit and writes back any additional status information to the status field in the currently selected
transaction description.
The data buffer associated with the iTD must be virtually contiguous memory. Seven page pointers are
provided to support eight high-bandwidth transactions regardless of the starting packet’s offset alignment
into the first page. A starting buffer pointer (physical memory address) is constructed by concatenating the
page pointer (example: page 0 pointer) selected by the active transaction descriptions’ PG (example value:
0b00) field with the transaction offset field. As the transaction moves data, the host controller must detect
when an increment of the current buffer pointer crosses a page boundary. When this occurs, the host
controller replaces the current buffer pointer’s page portion with the next page pointer (example: page 1
pointer) and continues to move data. The size of each bus transaction is determined by the value in the
maximum packet size field. An iTD supports high-bandwidth pipes via the mult (multiplier) field. When
the mult field is 1, 2, or 3, the host controller executes the specified number of maximum packet sized bus
transactions for the endpoint in the current micro-frame. In other words, the mult field represents a
transaction count for the endpoint in the current micro-frame. If the mult field is zero, the operation of the
host controller is undefined. The transfer description services all transactions indicated by the mult field.
For OUT transfers, the value of the transaction n length field represents the total bytes to be sent during
the micro-frame. Software must set the mult field to be consistent with transaction n length and maximum
packet size. The host controller sends the bytes in maximum packet sized portions. After each transaction,
the host controller decrements its local copy of transaction n length by maximum packet size. The number
of bytes the host controller sends is always maximum packet size or transaction n length, whichever is less.
The host controller advances the transfer state in the transfer description, updates the appropriate record
in the iTD, and moves to the next schedule data structure. The maximum sized transaction supported is 3
× 1024 bytes.
For IN transfers, the host controller issues mult transactions. It is assumed that software has properly
initialized the iTD to accommodate all of the possible data. During each IN transaction, the host controller
must use maximum packet size to detect packet babble errors. The host controller keeps the sum of bytes
received in the transaction n length field. After all transactions for the endpoint have completed for the
micro-frame, transaction n length contains the total bytes received. If the final value of transaction n length
is less than the value of maximum packet size, less data than was allowed for was received from the
associated endpoint. This short packet condition does not set the USBINT bit in the USB_USBSTS
register. The host controller does not detect this condition. If the device sends more than transaction n
length or maximum packet size bytes (whichever is less), the host controller sets the babble detected bit
and clears the active bit. The host controller is not required to update the iTD field transaction n length in
this error scenario. If the mult field is greater than one, the host controller automatically executes the value
of mult transactions. The host controller does not execute all mult transactions if:
MPC5125 Microcontroller Reference Manual, Rev. 2
32-88
Freescale Semiconductor