MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 707

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.4.1.21 Serial Interface Control Register (SICR)
This register sets the main operation mode.
Freescale Semiconductor
Address: Base + 0x50
Reset
Reset
ACRB
DTS1
Field
Field
AWR
RES
RTS
W
W
R
R
ACRB AWR DTS1
SPI
16
0
0
0
Assert RES output.
0 No operation
1 Negates output port RES, (RES becomes 1).
AC97. Reserved
Other Modes. Assert RTS output.
0 No operation
1 Negates output port RTS, (RTS becomes 1).
AC97. AC97 Cold Reset to the transceiver in PSC. This bit was prepared for backward compatibility with the
MCF5407 USART. It is recommended to use OP1 and OP0 registers to set and to reset AC97 reset line.
0 The transceiver recovers from low power mode in AC97.
1 The transceiver stays in the current state.
Other Modes. Reserved.
AC97. AC97 Warm Reset (to the PSC and off-chip AC97 Codec)
0 AC97 warm reset is negated. RTS output functions normally as the AC97 FrameSync.
1 Force 1 on RTS output, which is used as the AC97 FrameSync, and the PSC recovers from AC97 power
Other Modes. Reserved.
Codec. Delay of time slot #1.
0 First bit of first time slot of a new frame starts at the rising edge of FrameSync.
1 First bit of first time slot of a new frame starts one bit clock cycle after the rising edge of FrameSync.
Other Modes. Reserved.
MST
17
R
0
0
1
down mode.
Figure 25-38. Serial Interface Control Register for all Modes (SICR)
CPOL
18
0
0
2
SHDI
CPH
19
R
A
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
UseE
OF
20
Table 25-26. SICR field descriptions
4
0
0
Table 25-25. OP0 field descriptions
21
0
0
0
5
SIM[3:0]
22
0
0
0
6
En_O
utBuf
23
0
0
7
Description
Description
GenC
24
lk
8
0
0
0
I2S
25
9
0
0
0
ClkPo
10
26
0
0
0
l
Programmable Serial Controller (PSC)
Sync
Pol
11
27
0
0
0
12
28
0
0
0
0
Access: User read/write
13
29
0
0
0
0
ESAI
14
30
0
0
0
EnAC
25-29
97
15
31
0
0
0