MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 814

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
If the read transfer operation does not use DMA, the system needs to fetch data out of the data buffer
through utilizing the buffer read ready interrupt or by polling the STATUS[BUF_READ_RDY] status bit.
For high performance, data transfer using DMA is preferred.
28.5.5
Switch function command (CMD6) switches or expands memory card functions. Two function groups are
defined:
This is a new feature, introduced in SD Specifications Part 1 PHYSICAL LAYER Specification Version
1.10, so cards compatible with earlier version do not support this feature. Before issuing CMD6 to
switch-card mode, the host driver checks SD_SPEC field in SCR register to confirm the command is
supported. Card only accepts CMD6 in transfer state. After selected, all functions only return to the default
function after a power cycle, CMD6 (Mode 1 operation with Function 0 in each function group) or CMD0.
Executing a power cycle or issuing CMD0 causes the card to reset to the idle state and all the functions to
switch back to the default function. On responding to CMD6, the card sends R1 response on the CMD line
and 512 bits of status on the DAT lines. Therefore, for the host controller, this is like CMD17 for a single
block read with block size of 64 bytes. The time-out value of this command is also 100 ms. If CRC error
occurs on the status data, the host driver should issue a power cycle. CMD6 function switching period is
within eight clocks after the end bit of status data. When CMD6 changes the bus behavior, the host can use
the new functions then.
The software flow to enable high speed mode with DMA enabled is (assume SD_SPEC field is verified):
28-42
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1. Start MMC_SD_CLK if it is stopped.
2. Check the card status and wait until the card is ready for data.
3. Set the card block length to 64 bytes, using SET_BLOCKLEN (CMD16).
4. Set the SDHC Number of Blocks (SDHC_NOB) register to 1.
5. Disable the buffer ready interrupt, configure the DMA setting, and enable the SDHC DMA
6. Check the card status and wait until the card is ready for data.
7. Set the SDHC_CMD register to be CMD6(SWITCH).
8. Set the SDHC Command Argument (SDHC_ARG) register to 0x00FF_FFF1.
9. Set the SDHC Command Data Control (SDHC_CMD_DAT_CONT) register.
Card access mode: 12.5 MB/s interface speed (default) or 25 MB/s interface speed. (high speed).
Card command system: Standard command set (default), eCommerce command set, or Vendor
Specific Command set.
channel:
— Write 0 to bit[4] of the SDHC_INT_CNTR register in the SDHC to disable the buffer read
— Set DMA source to be SDHC_Buffer Access register.
— Set DMA source port size to be 32-bit.
— Set DMA burst length to be 16 bytes in 1-bit mode or 64 bytes in 4-bit mode.
— Set DMA transfer count to be 64 bytes.
ready interrupt.
Switch Card Mode
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor